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omap4 bootloader splashscreen for barebox

Honschu Lee
Prodigy 60 points

Hi

 I found no support for an omap4 bootloader splashscreen. So now I'm on to write one for barebox.

The display works great with Linux.

But in barebox (the bootloader) when I want to read register DSS_REVISION I get an error: "unable to handle paging request at address 0x48040000". This is what I'm trying to solve first.

The display is attached by LVDS to a FlatLink-Transmitter which is connected to the dispc2_* pins. No DSI is involved.

I already set the pin-muxing in barebox (bootloader) according to the muxing in the kernel and the barebox sets clocks already by default:

    /* Enable DSS clocks */
    /* PM_DSS_PWRSTCTRL ON State and LogicState = 1 (Retention) */
    __raw_writel(7, 0x4A307100); /* DSS_PRM */

    sr32(CM_DSS_CLKSTCTRL, 0, 32, 0x2);
    sr32(CM_DSS_DSS_CLKCTRL, 0, 32, 0xf02);
    sr32(CM_DSS_DEISS_CLKCTRL, 0, 32, 0x2);

    /* Check for DSS Clocks */
    while ((__raw_readl(0x4A009100) & 0xF00) != 0xE00)
        ;
    /* Set HW_AUTO transition mode */
    sr32(CM_DSS_CLKSTCTRL, 0, 32, 0x3);

Here are some register reads from barebox vs. linux (if you need more, please let me know):

barebox:
DSS_CM2 Registers (datasheet page 935):
! CM_DSS_CLKSTCTRL    0x4A009100 -> 0xE03
  CM_DSS_STATICDEP    0x4A009104 -> 0x20
  CM_DSS_DYNAMICDEP    0x4A009108 -> 0x0
! CM_DSS_DSS_CLKCTRL    0x4a009120 -> 0x00070F02
  RESERVED        0x4a009128 -> 0x70000
DSS_PRM Registers (629)
  PM_DSS_PWRSTCTRL    0x4A307100 -> 0x30003
! PM_DSS_PWRSTST    0x4A307104 -> 0x100030
  PM_DSS_DSS_WKDEP    0x4A307120 -> 0x80000
  RM_DSS_DSS_CONTEXT    0x4A307124 -> 0x103

  CONTROL_DSS_CONTROL     0x4A002340 -> 0x00000000
! CM_MPU_STATICDEP(817)    0x4A004304 -> 0xb0f0
! CM_MPU_M3_STATICDEP (901) 0x4A008904 -> 0x9070

linux:
DSS_CM2 Registers (datasheet page 935):
  CM_DSS_CLKSTCTRL    0x4A009100 -> 0x203
  CM_DSS_STATICDEP    0x4A009104 -> 0x20
  CM_DSS_DYNAMICDEP    0x4A009108 -> 0x0
  CM_DSS_DSS_CLKCTRL     0x4A009120 -> 0x60102 or 0x102
  RESERVED        0x4a009128 -> 0x70000
DSS_PRM Registers (629)
  PM_DSS_PWRSTCTRL    0x4A307100 -> 0x30003
  PM_DSS_PWRSTST    0x4A307104 -> 0x37
  PM_DSS_DSS_WKDEP    0x4A307120 -> 0x80000
  RM_DSS_DSS_CONTEXT    0x4A307124 -> 0x103

  CONTROL_DSS_CONTROL     0x4A002340 -> 0x00000000
  CM_MPU_STATICDEP(817) 0x4A004304 -> 0xA070
  CM_MPU_M3_STATICDEP (901) 0x4A008904 -> 0x60


What bothers me is that in barebox the register CM_DSS_DSS_CLKCTRL (0x4a00 9120) Field [17:16] IDLEST reads 0x3 which means "Read 0x3: Module is disabled and cannot be accessed". On linux, its 0x2 which means "functional".

I suppose that this is the problem why I can't read the DSS_REVISION register. Because the whole DSS "cannot be accessed" (?)! But I have no clue how to enable this DSS module.

Maybe you can give me a hint.

Thanks in advance

  • 0
    Expert 1780 points

    Hi Honschu.

    Modules have functional clocks (lets them do things) and interface clocks (lets you access their registers).  If the interface clock isn't running, you get a bus error when you try to read a register.

    Best guess is that you are missing CLKACTIVITY_DSS_L3_ICLK in CM_DSS_CLKSTCTRL.

    Note that you usually won't see the interface clock left on in Linux.  dispc_runtime_get() and dispc_runtime_put() are used to enable/disable the DSS interface clock just around the code that accesses the registers.  So you may not see it active when you happen to look at the register.

    Have you considered using u-boot -- the TI-standard bootloader for OMAP4?  It looks like a splashscreen for OMAP4 has been done with that:  http://e2e.ti.com/support/omap/f/849/t/197176.aspx

    Regards,

        Steve

  • 0 in reply to Steve Schefter
    Prodigy 60 points

    Steve Schefter said:

    Modules have functional clocks (lets them do things) and interface clocks (lets you access their registers).  If the interface clock isn't running, you get a bus error when you try to read a register.

    That's good to know. Thanks.

    Steve Schefter said:

    Best guess is that you are missing CLKACTIVITY_DSS_L3_ICLK in CM_DSS_CLKSTCTRL.

    Yes, the field CLKACTIVITY_DSS_L3_ICLK reads zero. In Linux and while the DSS is active, it gets one.

    But how to enable this DSS_l3_ICLK?

    I looked at TRM Figure 10-4 "DSS Clock Tree" (page 2108) and searched for a way to enable this clock. All I found was register CM_L3_1_CLKSTCTRL ( 0x4A00 8700 ) which reads 0x00000100. This means: "Corresponding clock is running or gating/ungating transition is ongoing".

    Steve Schefter said:

    Note that you usually won't see the interface clock left on in Linux.  dispc_runtime_get() and dispc_runtime_put() are used to enable/disable the DSS interface clock just around the code that accesses the registers.  So you may not see it active when you happen to look at the register.

    Thanks for the hint.

    Steve Schefter said:

    Have you considered using u-boot -- the TI-standard bootloader for OMAP4?  It looks like a splashscreen for OMAP4 has been done with that:  http://e2e.ti.com/support/omap/f/849/t/197176.aspx

    Thanks for the link. But I want to stick to Barebox.

  • 0 in reply to Honschu Lee
    Expert 1780 points

    Hi Honschu.

    Since the clock is enabled in CM_L3_1_CLKSTCTRL, best guess is that you are getting an auto hardware transition.  Stop that by setting CLKTRCTRL to 0 in CM_DSS_CLKSTCTRL.  You also need MODULEMODE in CM_DSS_DSS_CLKCTRL set to 2 to have interface clocks, but from the register dumps you provided that's already done.

    You can also monitor the ability to access the registers by looking at IDLEST in CM_DSS_DSS_CLKCTRL.  In your original register dump, IDLEST is 3 which means the interface clock is inactive.

    Regards,

        Steve

  • 0 in reply to Steve Schefter
    Prodigy 60 points

    Steve Schefter said:

    Since the clock is enabled in CM_L3_1_CLKSTCTRL, best guess is that you are getting an auto hardware transition.  Stop that by setting CLKTRCTRL to 0 in CM_DSS_CLKSTCTRL.  You also need MODULEMODE in CM_DSS_DSS_CLKCTRL set to 2 to have interface clocks, but from the register dumps you provided that's already done.

    You can also monitor the ability to access the registers by looking at IDLEST in CM_DSS_DSS_CLKCTRL.  In your original register dump, IDLEST is 3 which means the interface clock is inactive.

    Hi Steve, thanks for your input. I did the following based on your suggestion:

    mw 0x4A009100 0x0    #set CLKTRCTRL in CM_DSS_CLKSTCTRL to 0x0: NO_SLEEP: Sleep transition cannot be initiated.
    md 0x4A009100        #display CM_DSS_CLKSTCTRL
     output: 0x00000e00
    mw 0x4A009120 0x2    #set MODULEMODE in CM_DSS_DSS_CLKCTRL to 0x2: Module is explicitly enabled.
    md 0x4A009120        #display CM_DSS_DSS_CLKCTRL
     output: 0x00070002

    --> IDLEST: "Module is disabled and cannot be accessed"

    It's still the same behavior :-( DSS is not working.

  • 0 in reply to Honschu Lee
    Prodigy 60 points

    Finally I set CLKTRCTRL to 0x2 in CM_DSS_CLKSTCTRL which forces a software wak-up transition on the domain. And la voila, I can read the DSS register :-)

    Thanks for your inspiration Steve!