• State Resolved
  • Locked Locked
  • Replies 4 replies
  • Subscribers 45 subscribers
  • Views 692 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

About power-supply of LM965xx chipset

Konstantin Smirnov
Prodigy 20 points
Other Parts Discussed in Thread: LM96570

Hi, everyone.

Our team is working for portable ultrasound medical system design. We have to design extremely small system that is why we use LM965xx chipset. I've read datasheets of LM96570, LM96551, LM96530 and some posts: №1) http://e2e.ti.com/support/other_analog/imaging_afes/f/239/t/226250.aspx

№2) http://e2e.ti.com/support/other_analog/imaging_afes/f/239/t/258444.aspx

Also I've seen an electrical scheme of the TX-SDK-V1: 

№3) http://www.ti.com/lit/ml/snac053/snac053.zip

Nevertheless I have some doubts. So let me ask some questions.

Q1.  Rohit suggested to use the combination of 0.1uF+10uF capacitors between the pins VPF --> VPP & VNF --> VNN of LM96551 (see link №2). He also highlighted that the voltage rating for the capacitors should be around 100V. I can't understand this voltage rating. According to datasheet the difference between this pins is 10V. In the scheme (see link №3) I can see CB6=>0.1uF(0402) + CB6X=>10uF/16V (0805) capacitors. So, can I use capacitors with voltage rating 16V or 25V?

Q2. In the scheme of the TX-SDK-V1 (see link №3) I can see 0.1uF capacitors CB10, CB9, CB10A, CB9A (for example). All of them are connected to the pins which are close to each other. So my question is, can I use one 0.47uF or two 0.22uF capacitors to minify an occupied area? If not, why is it better to use 4 separate capacitors?

Q3. Following Q2, can I make the same changes with the capacitors: CC8 - CC9 - CC10, CC1 - CC2 and so on?

Q4. I can't find the capacitors CB9A, CB10A, CB6X, CB4X on the top layer of the TX-SDK-V1 (see link №3 -> User Guide -> Figure13). Are them on the bottom side?

It would be great to minimise a size of our system, but in the case if we won't minimise the quality of this one.

Thank you for your answers!

Konstantin

  • 0
    TI__Intellectual 1560 points

    Hi Konstantin,

    1) For the pins between VPP & VPF and VNN & VNF, you can use 16V caps.

    2) This is for minimizing the ESR. 4 might be an overkill. You might want to remove one at a time to see if there is performance degradation under worst case conditions (highest frequency and supply current).

    3) See 2 above.

    4) It should be on the bottom (I don't have a board to confirm).

    Regards,

    Charles

  • 0 in reply to Charles Guan
    TI__Intellectual 1560 points

    Hi Konstantin,

    Regarding item #4, I am able to a hold of the EVM, CB9A and CB10A are on the bottom layer. However, I can't find CB6X or CB4X on the board. I still recommend you put 10uF cap between VPP &VPF and between VNN & VNF. During CW mode, there is transient current on pins VPF & VNF.


    Regards,

    Charles

  • 0 in reply to Charles Guan
    Prodigy 20 points

    Hi Charles,

    Thank you for your answers.

    If you don't mind, I'd like to ask you some more questions.

    Q.5 Why is it important to minimize ERS (stabilisation or power consumption economy or another reason)?

    Q.6 Is there any recomendations for ESR?

    Q.7 You said that capacitors CB9A and CB10A are on the bottom layer. I think that such placement cancel ESR minimizing because of wire resistance and via inductance, doesn't it?

    Regards,

    Konstantin

  • 0 in reply to Konstantin Smirnov
    TI__Intellectual 1560 points

    Hi Konstantin,

    5) The reason you want to minimize the ESR is because during transient, the peak current on both VPF and VNF could be 1A (all 8 channels on).

    6) We don't have any official recommendation for ESR. But I would say 0.1 Ohm is a good start.

    7) The equivalent ESR won't be ESR_p1uF/4. But it should be better than ESR_p1uF/2.


    Regards,

    Charles