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AFE5809, demodulator and sync word

Other Parts Discussed in Thread: AFE5809

Hi,

I am working on a design with the AFE5809 and I see an odd behaviour regarding TX_SYNC_IN and the synchronisation word.

The FPGA interface with the AFE5809 is very similar to the one used on the TSW1200 evaluation board (see attached image from TI).

The AFE is configured initially with the demodulator off (the end system will be used with the demodulator on or off, so I am testing both operating modes) and a custom output word to configure the IDELAY for each channel independently. These are the register write operations to the ADC:

register 0x2 = 0x6000

register 0x5 = 0x156A

register 0x3 = 0x2000

register 0x4 = 0x0010

register 0x16 = 0x0001

The demodulator is then enabled with the following write operations to the demodulator:

register 0xDF = 0x8045

register 0xC2 = 0x6000

register 0xC5 = 0x55AA

register 0xC3 = 0x6800

register 0xC4 = 0x0010

register 0xCA = 0x1613

register 0xCB = 0x2772

register 0xE0 = 0x0001

register 0xE1 = 0x4000

register 0xCE = 0x0000

register 0xC0 = 0x0004

the FPGA interface is reset and synchronised again. The demodulator is then configured for normal operation with the following register write:

register 0xC2 = 0x0000

and the TX_SYNC_IN signal is generated with a frequency of about 15kHz.

The odd thing is that the behaviour of the first 4 channels is different from the last 4 channels. From the attached screenshots is possible to see a sync word (2772) at clock cycle 29 (yellow marker) on the last 4 channels, but not on the first 4. And there is a sync word on the first 4 channels at clock cycle 630 (white marker), but not on the last 4 channels.

The decimation factor is 5 and in fact for each channel there are: I sample, Q sample, 3 zeros. And when the sync word is present there are: sync word, I sample, Q sample, 3 zeros. I can see the correct sample pattern (sync, I, Q, zeroes) even at clock cycle 630 so it seems the demodulator sub-chip for channels 0-3 is really generating the sync word very late, but I don’t understand why and why the behaviour of the two demodulator sub-chips is different.

 

Best regards,

Matteo