AFE5809 test pattern generation problem

Hello Wei,

Thanks for using our AFE5809 device.
Before looking into your question, could you please let us know?
Are you using the AFE5809 EVM right now?
Also when you are using AFE5809 EVM, do you also together use TSW1400 EVM to capture data for AFE5809 LVDS output data?
We will try to run the same test as you did (as you mentioned)
using AFE5809EVM with TSW1400EVM.
and see if we can see the same behavior.

Thank you!

Best regards,
Chen

Chen,

We are using our own board design, not an EVM.  An update on our progress, we got the LVDS partially working (there was a bug in the FPGA that made it send wrong SPI commands, now that is fixed), D3 and D4 now appear to be outputting something, and when I set the test pattern to all 1 or all 0, the D3 and D4 LVDS lines stay at high or low as expected.  Now we have some more problems: 

- D2 and D1 LVDS outputs do not work, they appear to be stuck at 1 no matter what D3 and D4 are doing.

- Reading the registers on our FPGA, it looks like the AFE is not sending the sync word (0x2772), but we are not sure if this is the FPGA not reading properly or the AFE not sending a sync word.  If the LVDS is sending data, should it automatically send the sync word even under test pattern mode?

We are sending the following ADC register commands over SPI.

Addr 0x00: 0x0001

Addr 0x01: 0xC000

Addr 0x02: 0x6000

Addr 0x03: 0x2000

Addr 0x04: 0x0010

Addr 0x05: 0x3F80 (obviously this isn't used because addr 0x02 isn't set to custom, but we kept it anyways)

Addr 0x0A: 0x0100

Addr 0x16: 0x0001

I see the reason for why D2 and D1 LVDS outputs do not work. On section 8.6.1.2.8 of the datasheet, since we set the LVDS_OUTPUT_RATE_2X, it means D1 and D2 will not output anything.

The question then is about the sync word, under what conditions will the 0x2772 sync word be transmitted over the LVDS?

Hi Wei,

How are you?

We think because you need to use AFE5809's demod mode,

that is the reason you will use sync word. Right?

Using sync word, according to and following data sheet:

First, you need to set the register correctly, before you can see the sync word on LVDS output.

Sync word is used for you to recognize on LVDS output data, when you can receive the correct

data (such as A.I , A.Q , B.I , B.Q or '0000'=empty)

Please take a look (it also depends what kind of register you set to make M=3, or M=4, or M=5)

These are helping you to read data more correctly for using AFE5809 demod mode.

Thanks and best regards,

Chen

Chen,

Thanks for the reply. We managed to get the full chain "working" from analog input to LVDS output. When we input a sine wave to the AFE we can see data on the LVDS lines. I believe it should be safe to assume that the the sync word is embedded somewhere in there, however our FPGA is not detecting sync word and our FPGA PLL is not able to lock onto DCLK. Due to equipment bandwith limits, we are not able to see what DCLK is doing so we can't tell if it's the AFE sending a wrong DCLK or the FPGA PLL having an issue.

What we are trying to do is set up for 16 bit operation, DCLK 8x of FCLK, with sync_word 0x2772. Other functions are not important at this time, we just want to receive analog signals and output digital signals at 8x operation. The register settings we are using are below. Please let us know if this is not the right setting to achieve the functionality listed above.

addr 0x00: 0x0001
addr 0x01: 0xC000
addr 0x03: 0x2000
addr 0x04: 0x0010
addr 0x52: 0x117F
addr 0xC3: 0x6800
addr 0xC4: 0x0010
addr 0xCA: 0x0212

Thanks,

Wei-Han

Hi,

Is it possible to get some more detailed help regarding how to set the registers? I feel that I cannot adequately explain the requirement here and trying things out on my own is time consuming when perhaps somebody already knows the answer.

Thanks,

Wei-Han

Hi Wei,

Please let me try to contact some expert on the AFE5809 device very soon.

Sorry for waiting.

Thanks and best regards,

Chen

Wei-Han,

I am the applications engineer for the AFE5809 and I made the EVM and GUI, which I know that you are not using.  The sync word and also 16-bit mode only work when you are using the DEMOD feature. The ADC in the AFE5809 is only a 14-bit ADC, but the decimation can effectively increase the resolution to 16 bits.  Either way,  in any mode you can use the 16x serialization which is separate but similar to the ADC resolution.  For instance, you can use 14-bit ADC resolution and 16x serialization. 

So, please let us confirm the LVDS data without any use of the DEMOD function first, if you plan on using that.  Therefore, there will be no sync word in the data and we can use 14b,14x mode for the data.  This means that the FCLK will be at a frequency equal to Fs,  and the DCLK will be at 14/2 *Fs, or 7 * Fs.  If you can use a slower input clock than you can see if there is a speed or alignment issue, but I know that this is often difficult.

Please use the Deskew pattern to debug the DCLK alignment, and the Sync pattern to debug the FCLK alignment.

 

Chuck

Chuck,

We managed to correctly output a custom pattern with sync_word by having the ADC set to custom test pattern mode and the demodulator operating normally. This was just for testing purposes, for the actual system we need to make corrections.

I still have some confusion about the DCLK rate. For our project we are supplying a single-ended CLKP/N_ADC of 40MHz, combining LVDS output channels, 16x serialization, 4x decimation factor. We determined that this should result in an output data rate of 40MHz/4 * 32bits * 2 = 640Mbps on the combined channel. This would translate to DCLK of 320MHz, however, we observe that setting the register settings for LVDS 2x, 16x serialization, 4x decimation results in a DCLK of 640MHz. Could you clear up the confusion?

Wei-Han,

If you are using the DEMOD, then you should see the sync word when a trigger is applied to the TX_sync_in pin.

Data rate: This can confuse many people. Most ADC devices will reduce the output data rate with decimation. The AFE5809 is unusual because it does not reduce the output data rate (serial rate), but it does reduce the effective data rate and can interleave channels. Please see figure 67 of the datasheet. Whether the decimation is used or not, the serial rate does not change. If M=7, the serial output will be A.i, A.q, 0,0,0,0,0, A.i, A.q,.....In the FPGA, remove the 0s and deserialized the quadrature and the effective sample rate, Fs', for A.i will be Fs/7.

Fs=40MHz, LVDS 1x, Serz Rate =16x, and any Dec Factor : DCLK will be at FCLK*16/2, so 40M*8=320M. Divide by 2 comes from the DDR nature of the data, SDR would not divide by 2. Both clock edges can be used to latch the data in DDR.

For LVDS 2x mode, I believe the output data rate would double and there is 32 bits/FCLK instead of 16 bits/FCLK. Therefore, 320M * 2 =640M. Again, decimation does not help reduce this rate. With M=4, use the FPGA or processing device to separate the decimated data, throw away zeroes and de-interleave the channels, and each channel will have an Fs' = 10MHz, instead of Fs= 40MHz with M=1.

Chuck Smyth