TPS63070: Application questions

Hi Shinya:

Thanks for asking.

Your question involves a lot of details, I can't answer them clear, as I need to confirm the data with team. Please wait with patient for our discussion. 

Hello Shinya,

Please find my answers to your questions here inline:

1) Regarding the average current limit feature, it looks TPS63070 has not shutdown with hitting several over current threshold, but something like PWM modulated current limiting which drags down the output voltage, is it correct? 

The average current limit does not shutdown the device, but limits the average current from the input. As the load is drawing more power from the output than the input delivers, the output voltage falls down. As soon as the load is reduced, the voltage will rise again.

2) If 1) is correct, does the device still work switching until the output voltage drags below 1.2V of short circuit protection level?

Yes.

But it is possible that the overtemperature protection turn off the IC because of high power dissipation. It is as well possible that the high current causes the input voltage to drop and the UVLO is turning off the IC.

3) I'd like to estimate the worst case of the maximum load output current with the figure-20 on the datasheet. I think the figure can’t describe unit variation, but temperature variation only. How much variation we should multiply on it to estimate the worst case?

Figure 20 and 22 show the maximum load current of a typical unit with the external components given in Table 2. You are right that the process variations are not included. Process and temperature variations are included in the Electrical Characteristics of the Average, positive input current limit.
In your system I do not expect that you do not get more power than given by these figures at -40C as the device will heat up causing a reduction in available output current as the transistors are getting a higher resistance at higher temperature.

4) Regarding synchronization to an external clock mode;
  4)-1: Is there any problem toggling EN with staying PWM pulse input on the PS/SYNC pin?

No, these signals are independent from each other.

  4)-2: Do we need some delay time to wait for completing a synchronization? (e.g. XX clocks duration time is required after detected clock from low state)

The device switches seamlessly from the internal to the external clock and vice versa, so there is no specification for  the external clock detection. But the device needs some external clocks to be able to sync on them.

  4)-3: Which is the synchronization dtection trigger rising edge or falling edge?
  4)-4: Is there any duty rate limitation on the external synchronization clock input?

I will answer these questions later on. Latest beginning of next week I will come back to you.

Thank you so much for your support every time, Brigitte.

OK, I'm looking forward to seeing the rest of answers.

Thanks,
S.Sawamoto

Thanks a lot for the great help, Brigitte!

Regards,
S.Sawamoto