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TPS7H1101A-SP: Signal interface from current sense pin of TPS7H1101A-SP to analog input of ADC128S102QML-SP

SU ZHANG
Prodigy 210 points
Part Number: TPS7H1101A-SP
Other Parts Discussed in Thread: ADC128S102QML-SP,

Hi, 

I'd like to route the current sense signal at CS pin from TPS7H1101A-SP to ADC128S102QML-SP. My TPS7H1101A-SP design runs at 5V input, and ADC128S102QML runs at 3V analog power rail. Is it possible to use resistor ladder (without a buffer for voltage shift) to bring down the voltage level at CS pin to between 0V and 3V? what would the range of resistors be without affecting the current sense operation? with the input impedance of ADC128S102QML taken into account. 

Thanks. 

  • 0
    TI__Guru 62930 points

    Su,

    Let me research this, and get back to you.

    Regards,

    Wade

  • 0 in reply to Wade Vonbergen
    TI__Guru 62930 points

    Su,

    We had discussions regarding this and came up with idea that should be able to be implemented simply.

    Rather than potentially exposing the ADC input to CS voltage near the LDO Vin, you can use the RCS pullup to the 3.3V supply of the ADC.   This will prevent violating the absolute max conditions on the ADC.    The voltage across RCS can be adjusted accordingly by proper selection of the RCS value.

    CS pin also has absolute max constraints that indicate that it cannot be above Vin by more than 0.3V.  Thus, the 5V supply must come up first or simultaneously to the 3.3V supply  to insure that the CS pin does not get exposed to voltage greater than Vin +0.3V.

    It will likely be necessary to place additional capacitance on the CS pin to filter and  soften the load introduced by the 500ohm of the ADC and sample cap.

    You may also need to give the sampling cap more time to fully charge when reading the CS pin voltage.

    If this answers your question, please click "This Resolved My Issue"
    Regards,
    Wade

  • 0 in reply to Wade Vonbergen
    Prodigy 210 points

    Great idea. It's a simple solution indeed. Thanks. The 3.3V rail on ADC comes with soft start so it should always lag the 5V input rail. 

    I got everything you noted above, but I'm not sure about your last note. I suppose you meant the sampling cap inside the ADC128S102QML-SP. I am not able to find anything to manage the charging time in the datasheet. Can you please help me understand how to adjust the charge time for the sampling cap? Thanks. 

    You may also need to give the sampling cap more time to fully charge when reading the CS pin voltage.

    www.ti.com/.../snas411p.pdf

  • 0 in reply to SU ZHANG
    TI__Guru 62930 points

    Su,

    I am not very familiar with this ADC.  However, it does note that it has a 30pf capacitance with ~500 ohm impedance.

    If a capacitance is placed on CS that can be used to help charge the 30pf internal capacitance of the sample circuit within the 4 cycle track time, then this should work well.   I attempted to simulate the sample switch in the ADC with TINA, but something was not working correctly as I was getting impossible results.

    From a quick scan of the ADC datasheet, it appears that the track time is fixed with 4 SCLK cycles.  So, the only way to change this would be to lower SCLK frequency, or increase the capacitance on CS to provide more charge to ADC during the track time.

    Let me know if you still have questions.

    Regards,

    Wade

  • 0 in reply to Wade Vonbergen
    Prodigy 210 points

    Wade, thanks for sharing your thoughts on this. Understood. 

    Regards,

    =Su=

  • 0 in reply to SU ZHANG
    Prodigy 210 points

    Wade, 

    Sorry to re-open the ticket. not sure whether this would even show up as I chose to close it yesterday. 

    I'm wondering whether it's ok to tie the RCS resistor to 1.2V, as opposed to 3.3V on the ADC power supply. I'm asking because that is very easy for me to do on my board. I don't even need to run any wire. The 1.2V has soft start and comes up even after 3.3V, which comes after input 5V. 

    Please let me know, thanks! 

    =Su=

  • 0 in reply to SU ZHANG
    TI__Guru 62930 points

    Su,

    The ticket will automatically get opened back up, so no issue.

    Extending this down to 1.2V should work as well.

    You will need to make sure that the calculation for RCS are appropriate to insure that the CS pin stays in compliance across the full range of loads.

    Regards,

    Wade

  • 0 in reply to Wade Vonbergen
    Prodigy 210 points

    Wade, thanks for your comments. 

    if I make sure that Rcs * Ics < 1V (set to 1 to allow 0.3V margin), I think we should be ok. However, I realized that since 1.2V ramps up after 3.3V, so this might be a problem. We have a similar problem with connecting the Rcs to 3.3V as well if the 3.3V comes from the TPS7H1101A-SP output unless we carefully characterize the I/V over the ramp up period. Am I correct? 

    =Su=

  • 0 in reply to SU ZHANG
    TI__Guru 62930 points

    Su,

    I was able to get some time with the designer to discuss this.

    The threshold for CS disabling  foldback current is 90% of Vref (544mV).   The datasheet is currently going through an revision, and this will be made clear in the update.

    Below this value foldback will be disabled.   So, there should be some amount of margin above this to insure that foldback is not disabled unintentionally.  This may make it challenging to use pulled to the 1.2V rail.

    I am still checking on if there are issues with CS floating at power up.  Hope to get back on this shortly.

    Regards,

    Wade

  • 0 in reply to Wade Vonbergen
    TI__Guru 62930 points

    Su,

    I received my confirmation quicker than expected.

    The device will not have issue with CS not being pulled up immediately.   The foldback feature will be disabled until CS gets pulled above the 544mV threshold however.   It can be pulled up to the regulators own output.

    If this answers your question, please click "This Resolved My Issue"
    Regards,
    Wade

  • 0 in reply to Wade Vonbergen
    Prodigy 210 points

    Wade, thanks for the follow-up details on this. I appreciate it. that looks like a decent amount of margin and should do what I need. Thanks. =Su=