How to overcome spikes seen on LM25118 output

Hello
The LM25118 will operate with Vin = Vout.

Noise in a switching converter is caused as the switching devices are turned on and off and as the switched current is transitioned from one path to another. PCB layout is critical in reducing the amount of noise generated by these events and some information is given in the datasheet.

It would be worthwhile looking at the voltages at the switched nodes - either end of L1 in your case. If you see excessive ringing at the voltage transition then the layout may not be optimum. The options would be
1/ relayout the PCB
2/ Add snubber circuits at the switching nodes
3/ Add a second stage filter.
Filtering the output noise can be done with a second stage LC filter placed just before the output terminals.

Multi Layer Ceramic capacitors are a good choice for high frequency filtering BUT many low voltage types exhibit significant Voltage coefficient of Capacitance effects. For your 12V output, I would probably use some 0.1uF, X7R parts rated at 50V - check the manufacturers datasheet for the parts you are using.

Regards
Colin

Is there any further information you could give?

1) How would the PCB be layed out to be better? How much does the ground on pin 3 and 5 matter?

2) Please state specifically where and how you would put the R&C for the snubber you are specifying. Also state values based on what was given above.

3) Are 2nd-stage filters usually required? I added the 0.1uF, and it didn't really do anything. This seems like it shouldn't be required if the chip is working properly.

This has taken quite some time, and it's the only thing still not working on the board. Thank you.

Hi Brian

PCB layout is critical to implementing a design successfully - a good layout will be your friend, a bad layout will cause endless problems which you will probably require a re-layout to fix. Anyhow, this is all well and good.... there are many resources on the web which give information about SMPS PCB layout. Take a look at www.ti.com/.../sloa089.pdf and www.ti.com.cn/.../snva021c.pdf   for some basic information and there is a good article written by our friends in Linear Tech at    http://www.edn.com/design/components-and-packaging/4390811/PCB-layout-considerations-for-non-isolated-switching-power-supplies          , but the physics applies to TI based designs too !.

Anyhow, these all boil down to a few basic things -

Identify the nodes which are being switched and minimise the area of the tracks attached to these nodes. This is to minimise the capacitive coupling from these nodes into other parts of the circuit - Capacitance of course being proportional to the plate area.

Identify the loops which are carrying the switched currents and minimise their area. The relevant currents are identified in Fig8 and Fig 9 of the LM25118 datasheet but the return paths are implicit rather than explicit so I've drawn the full loops in the diagrams below. Note that the current loops differ between buck and buck/boost modes.

In Buck Mode the input current is pulsating (red only) and the output current (through D4) is present during both parts of the switching cycle (Red and Blue). The input current loop area should be minimised (drawn in Green). I haven't drawn the DC load or DC input currents of course.

In Buck/Boost mode, both the input current (Red) and output current (Blue) are pulsating - only the current in L1 is present during both parts of the switching cycle. This means that there are two current loops to be area minimised (Green)

The schematic shows the controller in the middle of the loops - this is the worst place to put it - the controller should be outside of the switched current loops and away from the switched nodes (M1_source, M2_drain etc.)

Physically - I would first place the components in the power circuit in as close to optimum fashion as possible. The components are Cin, Cinx, M1, L1, D1, D3, M2, D2, D4, Cout, Rsense.

Place the controller so that it is away from the switched nodes and outside the switched current loops - somewhere close to Rsense and near to or over a ground plane. It is VITAL to place the decoupling cap for the controller AS CLOSE AS POSSIBLE to the IC. If you don't do this, then the bootstrap capacitor, Cboot, may not get properly charged during the off intervals or the high side driver circuitry may not drive the M1 device cleanly. This will lead - at best to instant destruction of M1 or at worst - failure after 6 months in the field - with associated field replacement costs (that's why instant destruction is preferable)

You should make Kelvin connections to the current sense resistor - the chip provides inputs to allow this to be done easily (CSG and CS)

The AGND and PGND connections are important - Use a ground plane if at all possible to connect all the ground nodes of the circuit - this is easily done on a two sided layout - more difficult on a single sided layout.

I'm not personally responsible for the EVM PCB layout but from a quick look, it follows the guidlines above pretty closely - I would use it as a guide.

I also see the EVM doesn't include any snubbering components, so this may not be necessary in your design either. If you do need to add a snubber, then I would suggest a simple series RC network across D1/D3 and across D4/D2. It depends of course on what parasitics are causing the spikes in the first place. Component values for a snubber are pretty much always a matter of trial and error - difficult to predict, unfortunately.

A second stage filter is not required by the topology itself - sometimes one gets added, sometimes not. Now, In Buck mode the output current (in D4/D2) is continuous. This means that the output capacitor does not have to supply much additional filtering in order to keep the output ripple within bounds.

• I'm talking here about the current in the output loop as distinct from the LOAD current in Rload.
• By  output ripple, I mean the ripple at the switching frequency rather than the high frequency switching spikes.

In Buck/Boost mode however the output capacitor has to provide the load current during the interval when the current in the output loop is not flowing (ie, M1 is on - the red current is flowing, the blue current is off). The result is that you will need significantly more smoothing capacitance to keep the ripple within bounds when the system is running in Buck/Boost mode than when it is running in Buck mode - this is the condition that sizes Cout at 2 x 360uF

I would put placeholder pads on the PCB to take a LC fitler. Some thing like 0.1uF cap with a resonance at 1MHz or so - Measure the ringing frequency on the 'spikes on the output (I'd guess they are about 30MHz +).

Hope this helps

Regards

Colin

Brian

Here are the missing diagrams - e2e has a very funny way of attaching images - they were there on my original but they didn't upload properly - or at all.

Colin

A third attempt - here is the diagram for buck/boost mode