UCC27210 UVLO questions

HS FAE Germany

Other Parts Discussed in Thread: UCC27210

Hello,how is the UCC27210 behaving below UVLO (0-7V)? Are HO and LO high/low impedance? What about the range 7-8V (between VDD min and UVLO)?

Regards, Holger

over 7 years ago

0 John Stevens over 7 years ago

TI__Expert 7395 points

Holger,
Thank you for the interest. I've contacted the driver team to comment. You should here from them soon.
Regards,
John

0 Ritesh Oza over 7 years ago

TI__Intellectual 1875 points

Hi Holger,

Below UVLO, the output stage goes high impedance.

Unless, VDD reaches UVLO, the output is high impedance.

Regards,

Ritesh

0 HS FAE Germany over 7 years ago in reply to Ritesh Oza

TI__Mastermind 30505 points

Hello Ritesh,
customer has following concern: In case the boostrap voltage (Vhb-Vhs) is not high enough or not available during power up then the gate t of the HS Mosfet is not defined because the driver is high impedance. Further the LS Mosfet will switch the first time (half brigde is already under voltage) and that causes a short switching of the HS Mosfet through the Miller capacity and lead to a short of the half bridge. The available gate termination resistor of 10kohm will not help much.
This would be a big problem in LLC or primary HB applications.

To prevent this behavior customer thinks of using a clamping PNP Fet.

Regards, Holger

0 Ritesh Oza over 7 years ago in reply to HS FAE Germany

TI__Intellectual 1875 points

Hi Holger,

Yes, customer can place additional circuit.
Many of our customer do not need to put this circuit.
Generally the turn-on threshold of 100V MOSFET is higher than the spike that is generated on the gate of high side MOSFET, due to miller effect.
Layout and gate resistor, and type of power MOSFET also play important role in miller spikes.
I am confident but let me confirm with the design manger about the state of output pins in UVLO condition.

Regards,
Ritesh

0 Ritesh Oza over 7 years ago in reply to HS FAE Germany

TI__Intellectual 1875 points

Hi Holger,

I was wrong. I checked with our design team and they say that the outputs are hold active low when in UVLO, not high impedance.

Regards,
Ritesh

0 HS FAE Germany over 7 years ago in reply to Ritesh Oza

TI__Mastermind 30505 points

Hello Ritesh,
this sounds better. How is this technical realized?
You would need a gate voltage to switch on the transistors to get an low output in case of Bi-CMOS driver. In UVLO there may be no VCC and therefore the UCC27210 use hybrid driver (CMOS+BJT) or a parallel PNP switch? Please let me know how it works.

Regards, Holger

0 HS FAE Germany over 7 years ago in reply to HS FAE Germany

TI__Mastermind 30505 points

please send me an answer

0 Ritesh Oza over 7 years ago in reply to HS FAE Germany

TI__Intellectual 1875 points

I will let you know as soon as I get more details from design team.

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UCC27210 UVLO questions