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UCC28950: synch pin IO Characteristics

Part Number: UCC28950

Can you give additional information regarding Iin high and Iin Low of the synch pin when used in slave mode?  I am synchronizing several slaved converters to a master clock, but the typical logic i/o characteristics are absent from the datasheet with regard to the synch pin.  

App Note SLUA609 gives some VERY basic information to state the Vih>2.8V and Vol<0.5V for proper operation.   However, in order to know if I can meet those characteristics over temperature, I'll need to know the high and low input currents drawn by the synch pin.  I would like to drive the synch pin with the output of a  gate drive type optocoupler (HCPL0211), but the output of that device can sag as low as 2.4Voh under a few mA load.

It is very clear that UCC28950 loads the synch pin differently depending on it's enabled / disabled state.  When disabled, UCC28950 loads the synch pin such that the logic out of TTL devices sag substantially as compared to the enabled state.  None of this is described in the datasheet.

Regards,

Alex