Other Parts Discussed in Thread: UCC28060, UCC28063
I have a prototype 500W switcher using the UCC28061 as the PFC. My prototype has good harmonics performance at 50/60Hz but I am needing to operate over the avionics 360-800Hz as well. I have noted some degradation in the current THD as the line frequency is increased. This is most evident by a bump in the current just after a zero crossing. Refer to to the attached file
My suspicion as to the root cause is as follows:
1. The UCC28061 is applying the ADDITIONAL ON time as per figure 23 to compensate for MOSFET Cds etc. This is then fed into the PLLs
2. The zero crossing incurs a very large ADDITIONAL ON TIME and the PLL has a finite response time.
3. After the zero crossing has passed the PLLs take finite time to wind back to the correct ON TIME and hold the extended on time longer than required and as result the current is higher than expected occurs.
4. At 50/60Hz the PLLs are largely fast enough for this not to be an issue but not at 500Hz.
To test the idea I conceived a simple circuit where the VinAC pin was fed by the input voltage divider as normal but also I connected a extra high value resistor to this pin that went to a DC power supply. Hence I could tune this extra supply up and down to enforce a DC offset on the VinAC pin. This improved the situation markedly. I believe by doing so I have prevent the very large additional on times from being applied. As expected the more DC offset I applied the less the hump but the larger the flat spot as MOSFET Cds was not being adequately compensated for.
So some feedback on the following would be appreciated:
1. Does my logic sound correct?
2. If it is indeed a PLL slew rate issue can this be changed by any means?
3. Or is using the UCC28061 beyond 50/60Hz not a good idea? Any advantage in the UCC28060 or 28063? The differences as best as I can tell don't cover anything like this.
With the above modification I am almost in reach of reaching my harmonics requirements (which are notable tighter than EN61000-3-2).
