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UCC28089: About schematic problem

Satoshi
Guru 19575 points
Part Number: UCC28089

I made two type schematic but a few problem, please advice me below.

①In the below schematic, Output waveforms have small gap(about 80ns).

　Is there way to reduce timing gap for output?

②When VDD switch ON/OFF, on rare occasions OUTA and OUTB switching are reverse(inverted) polarity.

　Is there correction point?

Best regards,

Satoshi

  • 0
    TI__Mastermind 31580 points
    Hi Satoshi-san

    The dead-time is related to the discharge time of the Ct pin capacitor, I found this note in the datasheet which may help,

    "The oscillator is optimized for a CT timing capacitor range from 100 pF to 1000 nF and RB more than 100Ω. If the shortest discharge time possible is desired, it is permissible to short DIS to CT for all recommended CT values (100 pF to 0.100μF)"

    I suspect the polarity of the outputs on start-up are not controlled and the polarity can change on subsequent power cycles.

    Regards

    Peter
  • 0 in reply to Peter Meaney
    Guru 19575 points

    Peter-san

    Thank you for reply.

    About multiple control, these dead time occur not only OUTA and OUTB but also Master's OUTA and Slave's OUTA, is it correct?

    (Please see below waveform; Blue is master's OUTA, Green is slave's OUTA, timing delay is about 80ns)

    If no, is there way to reduce dead time(delay time)?

    If occurred reverse polarity, is there problem for UCC28089 operation?

    (Incorrect move, damage, etc)

    Best regards,

    Satoshi

  • 0 in reply to Satoshi
    Guru 19575 points
    Any update on this?
  • 0 in reply to Satoshi
    TI__Mastermind 31580 points
    Hi Satoshi-san,

    I have been out of the office last week and I had no opportunity to look at your recent question until now.

    How are the master and slave connected together ? I think the second circuit that you have with the two CT pins driven by a common sync signal will reduce the delay but there will be some variations in the timings between the master and slave due to variations between IC's.

    If the master and slave are driving two different power stages then there should be no problem if the polarity reverses following power cycling.

    Regards

    Peter
  • 0 in reply to Peter Meaney
    Guru 19575 points
    Peter-san

    Thank you for reply.
    Customer is agree to connect sync to two CT pins.

    About polarity, these are a need to align by customer application.
    Is there any Push-Pull IC(near UCC28089 series) for align polarity?

    Best regards,
    Satoshi
  • 0 in reply to Satoshi
    Guru 19575 points
    Peter-san

    Is there no device?
    I didn't find match device.

    Best regards,
    Satoshi
  • 0 in reply to Satoshi
    TI__Mastermind 31580 points

    Hi Satoshi-san

    I don't believe that any of TI's push-pull controllers have a guaranteed polarity on start-up. The only way to achieve this feature would be to use a micro-controller to generate the PWM signal or to use a signal from the micro-controller to some how gate the PWM drive signal to ensure the polarity is consistent for every start-up condition.

    Regards

    Peter