• State Resolved
  • Locked Locked
  • Replies 14 replies
  • Answers 2 answers
  • Subscribers 63 subscribers
  • Views 6113 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

UCC27714: Bypass cap 1uf VDD pin ferrite between COM & VSS, Cboot 10*Qg yet 100* more typical

Genatco
Guru 54568 points
Part Number: UCC27714
Other Parts Discussed in Thread: TIDA-00778, , MOTORWARE, TIDA-00195

Datasheet section 5 Pin configuration & functions: VDD 7 ---- Bias supply input. Power supply for the input logic side of the device and also low-side driver output. "Bypass this pin to VSS with typical 1-μF SMD capacitor (typically CVDD needs to be10 × CBOOT). If shunt resistor used between COM and VSS, then also bypass this pin to COM with 1-uf (1000nf) SMD capacitor."

We use a 20mOhm ferrite in series with COM/AGND providing higher frequency VSS digital ground isolation from AGND noise. That said the COM pin is tied to AGND plane and VSS pin DGND and no shunt trace feed back path to COM pin from low side NFET. Is a 1uf bypass still required on COM pin in that case and why not place 100nf bypass on VDD pin as other gate driver vendors typically suggest? Seems odd not to have 100nf

Regarding boot cap selection (application section 8.2.2.2) suggest 0.1uf (100nf) for 87NC Qg NFET. Is it not more typical a 1uf Cboot or (100*Cg=1000nf), but not 100nf? Thus 8.2.2.3 makes second odd claim VDD bypass (10*Cboot=1uf) seemingly should be 10uf, not 1uf. Either the (not guaranteed application section) formula works for all intended purpose or leads to questions as to why did application engineer change the earlier stated rules of UCC27714 in datasheet.. Perhaps a technical Wiki could help clear up some of these application questions.

Section 9 states 22uf 50v electrolytic on VDD supply pin, why not ceramic on VDD pin as datasheet section make clear (10*Cboot value) a best practice? Very confusing contradiction to earlier stated facts of VDD bypass requirement are being made in this section. Why not say VDD source requires 22uf electrolytic. If that is not true should each UCC27714 then have a 22uf electrolytic on the VDD pin?

Section 9 Power Supply Recommendations:

The VDD power terminal for the device requires the placement of electrolytic capacitor as energy storage capacitor, because of UCC27714 is 4-A, peak-current driver. And requires the placement of low-esr noisedecoupling capacitance as directly as possible from the VDD terminal to the VSS terminal, ceramic capacitors with stable dielectric characteristics over temperature are recommended, such as X7R or better.

The recommended e-capacitor is a 22-μF, 50-V capacitor. The recommended decoupling capacitors are a 1-μF 0805-sized 50-V X7R capacitor, ideally with (but not essential) a second smaller parallel 100-nF 0603-sized 50-V X7R capacitor. Similarly, a low-esr X7R capacitance is recommended for the HB-HS power terminals which must be placed as close as possible to device pins.

  • 0
    TI__Genius 12990 points

    Hi BP101,

    Thanks for your DS question, wiki feedback, and overall great additional info. I will update you asap with recommended capactiance on COM in your case, I have always seen VDD cap as being 1u and will look into the 100n claim. Can you send me the portion of your schematic that highlights the COM ferrite?

    I was able to see what you are talking about from e-cap recommendations in section 9. however, I dont understand what you mean with the contrasting info in section 8

    - 8.2.2.2 Selecting Bootstrap Capacitor - the calculated value is 100n

    - 8.2.2.3 Selecting VDD Bypass/Holdup Capacitor - the calculated value is 1000n

    It seems that section 9 is referring to the UG schematic below.

    Thanks,

  • 0 in reply to Jeffrey Mueller
    Guru 54568 points

    Hi Jeffrey,

    Jeffrey Mueller said:
    I was able to see what you are talking about from e-cap recommendations in section 9. however, I dont understand what you mean with the contrasting info in section 8

    The Cboot formula must work for all NFET selections (Cg) not simply the application and it seemingly fails to arrive at a proper Cboot value of 1000n. TIDA-00778 uses 1000n Cboot for a IGBT module and VDD bypass 10kn. Our prototype now use 1000n Cboot for NFET with Qg=103nC @15VDD and expected custom PCB with parallel NFET's produce roughly Qg=130nC to 174nC Max.  

    The 174QG & Cboot formula with 0.9v Dboot drop @1amp, +15VDD produced 123nf Cboot, seems an unrealistic RC time constant.  Is the application Cboot formula proven for all NFET pre-charge 1/2 bridge conditions as it seems to suggest we should use 120n for Cboot?

  • 0 in reply to Genatco
    Guru 54568 points

    Hi Jeffrey,

    I have reported TIDA-00778 design guide (Equation 12,13) conflict with UCC27714 datasheet application section equation for selecting Cboot RC time constant. It seems TIDA-00778 equation Cboot  jumps from 191n answer and designer then selecting 1000n Cboot with no explanation. Seemingly designer should have selected 200n or 0.22uf being the next readily available capacitor value for 274nC @VDD14.4v.

    Question remains which application formula produces the proper answer in all cases? 

    So if Dboot has 0.9v drop at 1 amp (per diode datasheet), we get 174nC/14.1Vdd*10 =123.4nf or 0.12uf Cboot for parallel NFETS in posted blue schematic. Suspect the diode & VDD drop will reduce with less than 1uf Cboot. Hence the lower QG of parallel NFETs with much faster rise and fall times than IGBT module coupled with a 4 amp gate driver should give excellent results if Cboot produce proper RC time constant. 

  • 0 in reply to Genatco
    TI__Genius 12990 points

    Hi BP101,

    I see, Thanks for making that clearer.


    There are a couple things to consider when choosing Cboot that are not taken into account with the formula from the TIDA and DS.
    The following factors are taken into account when finding Cboot Including switching frequency, load capactiance and VDD

    note power loss is proportional to switching frequency. Larger capacitive loads require more current to recharge the bootstrap capacitor, resulting in more losses. note The capacitor from VDD to COM supports both the low-side driver and bootstrap recharge. 

    The likely factor that differs the TIDA and DS calculation is due to dVboot as well as the total charge supplied by Cboot which is dependent on system factors like chosen FET and powertrain current.

    The equation Cboot = Qtot/Vboot can be used to find the maximum allowable voltage drop on Cboot to keep the HS-FET on during t_on.
    This can be done by factoring in V_GSmin. KVL produces: dVboot = Vdd - Vf - V_GSmin (where V_GSmin depends on the FET thats chosen)

    So, dVboot = Qtot/Cboot
    if the max allowable dVboot swing is 1V and Qtot = 130nC then 100nF Cboot will give you 1.3V dVboot which wont work
     with a 1000nF Cboot, Qtot=130nC and 1V of dVboot allowable swing gives only .13V of swing which will be more than enough.

    <Figure 36 from the TIDA explains that the dutycycle was 80% and the dVboot was only .5V>
    <DS parameters for dutycycle and dVboot appear to be less>

    Also, duty cycle can be seen to affect Qtot with the following equation

    The total charge supplied by Cboot is not just Qg: (LK is leakage current)
    Qtot = Qg + (I_LKGS + I_LKCAP + I_LK + I_QBS + I_LKdiode)*t_on + Q_LS

    Does this make sense? would you like me to confirm this with the designer for you to confidently proceed?
    Thanks

  • 0 in reply to Jeffrey Mueller
    Guru 54568 points

    Hi Jeffrey,

    Jeffrey Mueller said:
    There are a couple things to consider when choosing Cboot that are not taken into account with the formula from the TIDA and DS

    Agree yet that is not being elaborated in the simplified formula and the designer TIDA makes a huge leap Cboot value with no explanation of why, leaves many questions unanswered. 

    Jeffrey Mueller said:
    dVboot = Qtot/Cboot

    What is dVboot, the drop across diode?

    Jeffrey Mueller said:
    <Figure 36 from the TIDA explains that the dutycycle was 80% and the dVboot was only .5V>

    That 0.5v Cboot ripple (bump) occurs as VDD returns from sag, each time low side NFET turns off, not on. Seems the designer does not make that clear yet Tina transient analysis makes that very clearly noticeable.

    Jeffrey Mueller said:
    if the max allowable dVboot swing is 1V and Qtot = 130nC then 100nF Cboot will give you 1.3V dVboot which wont work

    Tina UCC transient analysis with 120n Cboot the drop appears as (mv) difference to that of 1000n in dVdrop other than dVboot drop is reduced. Similar 2 amp dVboot peaks remain in each NFET ton cycle both tested values 120n-1000n of Cboot. What really changes as seen from the 2 Tina analysis is the ripple current across HB/HS pins is reduced @1000n Cboot.

    Jeffrey Mueller said:
    The total charge supplied by Cboot is not just Qg: (LK is leakage current)

    Perhaps a need for more Cboot formula factors included in DS? The application Cboot formula appears all relative for UCC gate driver designs, no other input required. Other gate drive vendors provide a separate technical disclosure with formulas to elaborate Cboot RC time constants and or anomaly WA's. Perhaps a Wiki would be highly beneficial it seems from the added info of leakage current. Though has little if any effect on Cboot (ceramic), is not even valid formulas of other gate driver vendors. What works now with current vendors gate driver may not behave the same with TI gate driver, who really knows if it ain't being disclosed in DS text design guide sections.

    Still like to know if require a 1uf VDD bypass to AGND with ferrite chip 20mOhm DC(120Ohm @100Mhz) shown in schematic, (Omit 1uf)? Our custom PCB will have a 22uf ceramic on VDD 500ma buck down and 10uf holdup on each UCC driver. That would seem enough reserve and 22uf electrolytic was perhaps an afterthought? What of placing 100n bypass UCC  VDD pin in lieu of 1000n to AGND?  

     

  • 0 in reply to Genatco
    Guru 54568 points
    Perhaps the DS & TIDA-00778 formulas used to calculate Cboot value incorrectly multiply Cg*10, since Cg*100 produces far less Cboot ripple HB-HS. At least at 12.5Khz 80us periods that seems the case VdBoot (VD1) has fewer periodic -spikes and VHB overshoot peaks are thus reduced as a result of less HB-HS ripple.

    So Cg*100 in DS application would produce 760nf versus 76n Cboot in that case.
  • 0 in reply to Genatco
    TI__Genius 12990 points
    Hi BP101,

    Sorry for the delay in my reply. Thanks for the great TINA explaination! I understand your concern.

    -I will ask the designer of the TIDA why Cboot=Cg*100.

    -as well as why the 22uF VDD afterthought.

    -I will then give you advice from my team on whether or not you can get away with 100nF bypass from VDD to AGND instead a 1uF on COM when using the ferrite.

    Let me update you on Monday.
    Thanks
  • 0 in reply to Jeffrey Mueller
    Guru 54568 points

    Hi Jeffrey,

    Thanks for the update.

    I added pads for a 22uf 50v electrolytic placed near 1st of 3 UCC on +15 bus. Do relate to APP designers concern as currently have a ceramic cap on +15 boost regulator and 10uf 25v AL electrolytic +15v bus roughly 2" away from boost ceramic and only 100nf hold up on each gate drivers VDD pin.

    Seems DS & TIDA (Cg*100) might produce better results ? and that perhaps depends on the PWM frequency and total Qg. It also plausible 100Khz & up PWM might not suffer as much @ Cg*10. From my understanding TIDA-07788 was tested at 15kHz-20Khz PWM. Oddly UCC27714EVM-551 does not mention the PWM frequency nor does DS 600 watt power supply application section.

  • 0 in reply to Genatco
    TI__Genius 12990 points

    Hi BP101,

    I was not able to get in touch with the designer yet, however my team gave me their thoughts.

    The DS uses a PWM of 100kHz in the example and The TIDA uses PWM of 5-20KHz.The EVM users guide does not specify frequency however they give a bode for 100Hz-100kHz.


    5-20kHz -> is relativly low switching frequency -> plenty of time to charge the cap

     for the TIDA the designer likely thought since, for some reason, there was more noise in this system, the HB-HS would sag in certain line-load conditions with a cap value lower than 10uF.


    if your application uses more than 100kHz then there will be more noise (from layout as well) and since you wont have too much ripple or dip then you can get away with the 100nF Cboot like the DS.

    as for the 22uF - in the TIDA the VDD bias is generated with external power supplies (and in your circuit is generated differently) which may not have a e-cap or noise free VDD.
     -> the designer thought 10uF was not enough to hold VDD steady with minimal ripple while charging the bootstrap. If you think your VDD is fine then you dont need 22uF.


    Can you tell me any of the following info?

    1) what is your allowed bootstrap ripple (dVboot)?

    Cboot > Qtot/dVboot


    2) minimum duty cycle? 

    Dmin = (Qg*f + Ileak)(Rboot/dVboot)


    3) max PWM frequency?

    Dmin > 4*Rboot*Cboot*f


    4) required time constant, tau?

    tau = Rboot*Cboot/D


    Let me update you with 1u vs 100n with the ferrite question. As well is direct input from the designer.

    Thanks

  • 0 in reply to Jeffrey Mueller
    Guru 54568 points

    Hi Jeffrey,

    Jeffrey Mueller said:
    5-20kHz -> is relativly low switching frequency -> plenty of time to charge the cap

    Agree and even more time for it to discharge making the 1000n produce less ripple at lower frequency than 100n as Tina also proves the case.

    Jeffrey Mueller said:
    for the TIDA the designer likely thought since, for some reason, there was more noise in this system, the HB-HS would sag in certain line-load conditions with a cap value lower than 10uF

    Yet the DS power supply application uses the very same 10uf holdup on VDD but the TIDA used external 50ma +15 supply which I question the design required only 50ma external VDD supply and producing 2 amp peaks in HO/LO gate drive seemed out of place. The cost and board space required for adding 10uf hold up caps seems misplaced for production environments seeking to reduce design costs and or parts count. A typical +15v buck down regulator can easily produce 500ma without a second thought. That alone confuses the issue to have 5.1R plus 10uf hold up and 1uf VDD-COM for any design purpose lest of all an additional 22uf e-cap. Perhaps a 1000n VDD bypass is only required if COM is relatively above VSS otherwise 100nf might be a better solution when COM ties to VSS without a shunt or a dedicated trace route from shunt leading back to COM pin.  TIDA seems to blur the DS requirement for 1000nf bypass by adding the trace route from the shunt above VSS. Designer never explains the electrical advantage of using extra board space for a dedicated trace route from the shunt back to COM when the DS seems to directly contradict any such practice.

    Jeffrey Mueller said:
    1) what is your allowed bootstrap ripple (dVboot)?

    What ever a proper formula produces for Cboot RC time constant based on the PWM frequency of Ton. 1000nf seems to work ok at 12.5kHz-20kHz. Again the point is the formula in the DS application seemingly is not considering the PWM frequency or the variable duty cycle.

    Jeffrey Mueller said:
    2) minimum duty cycle? 

    The PWM duty is highly dynamic and roughly 30% during Cboot pre-charge time (0-1000ms) if choosen to and grows from 0%-98% relative to increasing rotor velocity until steady state velocity is reached. Much unlike a switching power supply the low side MOS near 100% duty in slow current decay of high side MOS of co-phase partner 1/2 bridge. That is why it is difficult to simulate actual real Cboot cycles in Tina with only one UCC. Perhaps the formulas that relate to power supply design seem to fall apart in 3 phase motorware 1/2 bridge designs.    

     

    Jeffrey Mueller said:
    4) required time constant, tau?

    That is a new one on me,, seemingly 1/2piRC would be a simpler formula to determine the R/Cboot discharge rate based on the Astable frequency required to keep HB floating above COM.

  • 0 in reply to Genatco
    TI__Genius 12990 points

    Hi BP101,

    The response from the designer was that the IGBT used in the TIDA has higher gate charge than DS. Also VDD cap was chosen proportional to Cboot and was taken to be more than 10 times Cboot. I will update you after I do a followup question to clarify.

    The reason why you would use 100n vs 1000n on VDD is smaller caps are used to more effectivly filter MHz high frequency noise riding on the kHz ripple. This is the cap that is supposed to go as close as possible to the IC to mitigate trace inductance. In order for the larger VDD ecap of 22u and 10u to charge the bootstrap quickly these also have to be close.

    Thanks,

  • 0 in reply to Jeffrey Mueller
    Guru 54568 points

    Jeffrey Mueller said:
    The response from the designer was that the IGBT used in the TIDA has higher gate charge than DS.

    Relative to Cg = 100 times and not 10 times as the both documents make a point of fact in stating. Yes I agree the IGBT has a greater gate charge requirement but only during Cboot pre-charge time does that seem to be an significant issue. Tina transient analysis seems to argue against the need for Cg*100 our case 170nC maximum. Perhaps the 5.1 VDD resistor 10uf hold up is bottle necking HO/LO drive current, making it appear as if 1000n Cboot is necessary?  

    Jeffrey Mueller said:
    The reason why you would use 100n vs 1000n on VDD is smaller caps are used to more effectively filter MHz high frequency noise riding on the kHz ripple

    The other vendors gate driver chip used 100nf for VDD to bypass fast transients to ground, thus my confusion to see 10uf and no 100nf on VDD. Oddly VDD isolation method via 5.1 ohm seemingly limits HO/LO outputs to 2.94 amps, so how could HO/LO ever reach 4 amps drive capability for long from a hold up cap on VDD alone?  That is very conservative being the gate drive source/sink resistance is not being factored into drop in VDD current due to 5.1 ohms and totally relies on the 10uf hold up capacitor (distant 22uf e-cap) for all drive current exceeding 2.94 amps. Might be a good reason why the TIDA captures of gate current (figures 33-25) spike +/- for very short periods just reaching 2 amps peak. Yet equations 16-19 suggest 2.63-2.74 amps sink HO/LO for switch node turn off current limits for the IGBT module. Tina was indicating near 3 amps peaks HO/LO with 6/12 ohm gate drive resistors without a 5.1 ohm in series with VDD.

    Why do we limit the VDD pin 10uf hold up to 2.94 amps from VDD power supply source?

  • 0 in reply to Genatco
    TI__Genius 12990 points

    Hi BP101,

    To follow up from my last reply,

    Each UCC27714 has a separate 10uF in TIDA-00778 as per the datasheet recommendation.
    The input 22uF ecap (recommended in DS for 4A peak) is to stabilize the input 15V supply coming externally. 
    If the external power supply has long wires, then this 22uF will help to stabilize this.

    For a shunt on COM to VSS: 1 uF is the recommended value in the datasheet. 100n can work depending on the layout.
    The sense resistor will cause voltage transients during switching and if it is not crossing the limit (+/- overshoot) with a good margin, we are good. 
    1 uF will give a better stability against such transients.


    The +/- 4A HO/LO drive capability is given in the DS for a pulsed current of 100ns. The 5R in series with bias VDD is recommended in the DS.

    I will have to update you on how this limits peak current drive capability.

    "Why do we limit the VDD pin 10uf hold up to 2.94 amps from VDD power supply source?"
    where in the TIDA are you getting 2.94A value from?

    Thanks,

  • 0 in reply to Jeffrey Mueller
    Guru 54568 points

    Jeffrey Mueller said:
    The input 22uF ecap (recommended in DS for 4A peak) is to stabilize the input 15V supply coming externally. 

    That is a 600 watt 50 amp power supply and it sources VDD from an external source, seems very dangerous especially with off line hardware. I buy the idea a remote 22uf e-cap would help to filter trash near UCC feeding back on the VDD supply through the 5.1 R and to give some overall stability during heavy current surging of VDD pin. 

    Jeffrey Mueller said:
    For a shunt on COM to VSS: 1 uF is the recommended value in the datasheet. 100n can work depending on the layout.

    Yet it seems odd to see a 100nF parallel with 10knF and 100n is not even present in the DS application without a shunt 

    So it would appear when a shunt is not located (directly) between VSS and COM then 1000n is not required and perhaps will do little in that case to arrest shunt noise on VDD. Seemingly the DS should advise, e.g.100n replaces 1000n when otherwise a shunt is not located (directly) between COM - VSS???? 

    Jeffrey Mueller said:

    The +/- 4A HO/LO drive capability is given in the DS for a pulsed current of 100ns.

    Actually it seems 4 amps 100ns is highest frequency Max current and low frequency (IGBPK pulsed short circuit sink/source HO/LO = PW<10us or 100kHz @4AP). Notice the 100n is in the AMR top list and 10us EC list seems to suggest 4 amps at 100kHz is an expected behavior.

    Jeffrey Mueller said:
    "Why do we limit the VDD pin 10uf hold up to 2.94 amps from VDD power supply source?"
    where in the TIDA are you getting 2.94A value from?

    A capacitor can quickly discharge current when it sinks beyond the input supply ability and voltage periodically falls & rises rapidly. It would seem for a Hold cap to source 4 amps @15v for 30-80us Ton the VDD resistor must be much lower or perhaps .707 of peak is the expected RMS current of HO/LO pins? Seemingly IGBK is 4*.707=2.82 ARMS with 5.1R ???? and Peak IGBK then factors as R=E/I or 3.75R=15VDD/4A and not 5.1R. Oddly the 22KW TIDA-00195 uses a 10R in series with VDD & 100n hold cap and sinks near 3.25 amps @1us (fig30-33). Hence my questioning 5.1R limiting peak VDD cap hold current to 2.94 amps in extend Ton periods well beyond 1us may lead to NFET premature current avalanche.

    By what formula was 10kn hold cap 5.1R determined to produce an 80us-85us maximum Ton @4amp gate current via VDD pin? We expect to peak near 8KW and it seems hard to imagine possible in this case.