I'm laying out with the WQFN version of the LP5521, and the first thing I notice based on the datasheet is that the CFLY pins are interlaced with each other. The ordering is 2N, 1N, 2P, 1P, whereas for even the most basic of layout sanity it should be 2N, 2P, 1N, 1P. This means I am forced into significant contortions in order to actually hook up the capacitors, rather than just laying them out adjacent to each other and routing the pins. Given that the layout section makes a big deal about keeping the traces from the chip to the capacitors short and to the point, we have a problem....
Before I get any further, I need to make sure whether this information is actually correct or not. If the datasheet is indeed accurate, I need somebody to *SMACK* the designer...
