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About DR pin of LM3488-Q1

Masami Michino
Genius 5070 points

Dear, All

The case where the D-G terminal of FET linked to DR pin of LM3488-Q1 short-circuits is examined.
The voltage of Vin is usually 12V and a maximum of 36v.
For this reason, the voltage by which a seal of approval is carried out to DR pin is a maximum of 36v.
In this case, is LM3488-Q1 destroyed?

Thanks, Masami M.

  • 0
    TI__Intellectual 770 points

    Hello

    The datasheet in section 'Absolute Maximum Ratings' mentions DR Pin Voltage should be between -0.4V to 8.0V,  hence exceeding this voltage is not recommended.

    Regards,

    Doyel

     

  • 0
    TI__Genius 16025 points

    Hi Masami,

    As long as the DR pin doesn't exceed 8V you are fine as Doyel mentioned. However for a Vin of 12V to 36V there should be no problem specifically because this is not a D-G voltage. I think the point of the Abs Max is to mention that the DR pin should not make accidental contact with anything above 8V, which in this case can only happen with a D-G short. This is very unlikely and most FET failures happen between Drain and source.

    Thanks,

    Anston

  • 0 in reply to Anston Lobo
    Genius 5070 points

    Hi, Anston-san and Doyen-san,

    Thank you for your reply.
    I answer it to a customer.

    Thanks, Masami M.

  • 0 in reply to Masami Michino
    Genius 5070 points

    Hi, Anston-san

    The customer is examining failure mode when it is considered as D-G short-circuit of FET.

    About D-G short-circuit of FET connected to DR pin of LM3488-Q1, the customer has an additional question.
    Please teach me the view point by which the protection circuit when the above-mentioned conditions occur is not contained in LM3488-Q1.
    For example, since it does not result in DR pin destruction of LM3488-Q1 even if D-G short-circuit of FET occurs?
    etc,
    Thank you for your consideration.

    Thanks, Masami M.

  • 0 in reply to Masami Michino
    TI__Genius 16025 points

    Hi Masami,

    I completely forgot to mention this is a Low Side N channel FET driver. The importance here is it is "Low Side" only to enable Boost and other step-up topology. As a result, the Low side FET will never see Vin or 36V. Rather the maximum voltage will be VCC. Even if D-G short occurs, the device will internally switch off the DR pin if it detects any abnormality. This is detailed in the protection features of the IC in the datasheet. Hence the DR pin has no reason to be spec'd at anything above 8V.

    Thanks,

    Anston