LM3488 – Question regarding the input clock SYNC signal. The datasheet says that the SYNC input duty cycle must exceed the maximum duty cycle period.
Customer is running the part, nominally, at 250kHz (4uS period).
Two applications: 18V-40V VIN à 50V output (71%), 18V-40V Vin à 90V output (84%). SEPIC topologies.
Each one will require a period-high of 2.84uS and 3.36uS respectively… but their clock source is typically 50% duty-cycle, +/-10%.
Additionally, the datasheet says that the SYNC cannot exceed 10uS or we shut the part down (Should not be a problem here).
So – what’s the best way to tackle this duty cycle requirement? I think part of the issue is that this 250kHz clock goes to multiple DCDC converters and they don’t want to mess all the others up for these two ICs (LM3844).
Regards,
Aaron
