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[TPS62130A-Q1] Conducted Emission FM Frequency Noise

Other Parts Discussed in Thread: TPS62130A-Q1, TPS62130A

Hi,

I'm using TPS52130A-Q1 in the power management of a device. The PCB layout has been taken directly from Webench. But there are some issues during Conducted Emission Test for CISPR 25. The average for 96Mhz in the FM Band is more than standards of Class 2. Rest of the frequencies are upto standards till Class 4. This seems to be a harmonic of the switching frequency of 2Mhz.

I would like to know whether this is normal as there is no filtering in the design?

Also are there any recommended filters and layouts for the design which can help in reducing these noises? I have looked at some CISPR 25 Class 5 reference designs, so if there is similar one for TPS62130A-Q1 or some recommended parts for the same, please share.

I'm posting the layout images for reference.

  • Hi,

    The webench tool is a very good starting tool but the exported layout is not for best EMI performance.
    TPS62130EVM layout is better: www.ti.com/.../TPS62130EVM-505. You should also have a look in the DS for our layout recommendations.
    Why do you changed your layout compared to your other thread?

    You should shrink the switch node plane of the inductor. It is very big on the webench export to place different sized inductors.

    It looks like your GND header is not connected to the GND bottom layer. Now the input current return path is only connected through some vias and fairly long. You could try to add a thick wire from the GND header to the GND of the input capacitor. This should already help.

    Beside of that you can add some components on the input to filter out the 96Mhz noise. A High frequency capacitor or a LC combination.

    Could you share the part number of the inductor you use?

    It looks like you want to connect the board to the 12V car battery? If yes, you will need an over-voltage protection in front of the board.

    Thanks & Regards,
    Michael
  • Hi,

    Thanks for the reply.

    Reason for changing the layout is that now this power board is a separate one so that we can do revisions easily without disturbing the rest of the system.

    Thanks for pointing about the switch node plane of inductor. I will do that.

    I don't understand what you mean by GND header. If you are referring to the PGND not connected to GND, then noted. If not, please explain.

    The inductor part number is  SRN8040-2R2Y . It was suggested by Webench.

    Yes, the circuit will be connected to car battery. I am adding the over-voltage protection in the new revision. I'm using this guide. Please provide suggestions on the same.

    Regards

    Lalit Kumar

  • Hi,

    It looks like your input GND connector is not connected to the GND plane on bottom layer.
    It is only connected on the top layer.
    Now the input current return path is only connected through some vias and fairly long.
    You could try to add a thick wire from the input GND connector to the GND of the input capacitor.

    Yes, you should connect PGND and AGND to the thermal power pad below the IC.

    As per DS the inductor is not fully shielded. I would recommend to use a shielded one for best EMI performance.

    Beside of the guide you could use following OVP reference design: http://www.ti.com/tool/PMP9757

    Thanks & Regards,
    Michael
  • Hi,

    The input GND connector is connected on both the layers, as the connector is PTH.

    I will change the layout to decrease the return path and connect PGND and AGND directly.

    I thought semi-shielded would work. Will replace it with fully shielded.

    Will look into the guide and change the layout and share here for feedback.

    Thanks for the support.

    Regards

    Lalit Kumar

  • Hi,

    I'm attaching the new schematic, layout, BOM and gerber files for reference. Please provide suggestions.

    I talked to regulatory body in my country, India, they said that the regulation states over voltage protection of 100V and -100V reverse voltage protection. I have replaced the parts accordingly.

    Regards

    Lalit Kumar

    power.zip

  • Don't forget to up load your files...
  • Hi,
    I have uploaded a zip containing all the files.

    Regards
    Lalit Kumar
  • Hi,

    thanks for sharing the files.

    Please follow our layout recommendations in the DS page 27.
    Place the input and output capacitors as shown in figure 50.
    In your current layout the placement is not ideal. The input loop is the most critical path of a buck converter.
    Here is a paper which describes a good layout step by step for the TPS62130A: www.ti.com/.../slyt614.pdf

    Thanks & Regards,
    Michael
  • Hi,

    I've followed this layout as mentioned previously. The layout differs a lot from what is provided in the datasheet. Please clarify which one I should follow for better performance.

    Regards

    Lalit Kumar

  • Hi,

    I'm attaching the modified layout at the bottom.

    I have made some extra changes:

    1. Cutout the ground below inductor.

    2. The power GND and signal GND is connected in top layer. Should I isolate the power GND?

    3. The EN of Buck is connected to overvoltage protection circuit. I have routed that from below Input Capacitor without cutting the VIN and GND plane. Is that right?

    4. The VIN and VOUT planes are very large. It is written that only SW plane should be small. Should I reduce other planes too and use a thick trace or current layout is right?

    As for my previous post, I misunderstood the gerber files. Sorry for the misunderstanding.

    Regards

    Lalit Kumar

    5773.power.zip

  • Hi,

    Please provide feedback in the new layout.

    Regards

    Lalit Kumar

  • Hi Kumar,

    sorry for my late response and the confusion.
    For best EMI performance it is key to place the input capacitor as close as possible to the device inputs as shown in the DS and described in more details in following paper: www.ti.com/.../slyt614.pdf

    Your current layout looks fairly good now.
    Here my recommendations:

    - Connect the signal/analog GND to the power GND directly under the device at the thermal pad only.

    - Route the AVIN trace to CINx isolated from VIN. (like in the paper above - figure 5)

    - Place additional pads on the device input (in parallel to CIN). Then you can easily add some additional capacitors during your test phase.

    Thanks & Regards,
    Michael