Rise time of output voltage TPS56C215

Hi,

It's only the soft start time. Vout start ramping after the MODE setting reading is completed.

Vincent Zhang

Thank you for your help!

Is my understanding correct as follows?

Tss is the time from IC enables to ramping output voltage.
Tss does not consider time of Vreg5 and MODE.

Best regards,


Takahiro Nishizawa

Hi,

'Tss does not consider time of Vreg5 and MODE' is right, but Tss is only part time from IC enables to ramp output voltage.
The time from IC enables to Vout completely ramped is also included 'the VREG5 RAMP' time and 'MODE setting' time.

Vincent Zhang

Thank you for your answer!

I have a question about Figure.27 datasheet p.17.

Please tell me the maximum rising time of VREG5 when VREG5 is 4.3V.

Best regards

Takahiro Nishizawa

Thank you for your help!

How is your the situation?
I am waiting for your answer.
I expect your early reply.

Best regards


Takahiro Nishizawa

Hi,

Sorry for the delay. We don't have the maximum rising time in database. But I test from 5-12VIN->1V, from 0A-12A on EVM, the rising time is about 600uS. Hope it will solve your questions.

Vincent Zhang

Thank you for your answer!

Do you tell me the ramp time of VREG5 under the following conditions by your EVM?

Vout=4.3V


Best regards,


Takahiro Nishizawa

Hi,

It's tested at 1VOUT condition. 600uS is the time from VIN rise to 1.2V to VREG5 rise to 4.3V as Figure 27 described.

Vincent Zhang

Thank you for your answer!
Is my understanding correct as follows?

If Vout changes, VREG5 does not change.


Best regards,


Takahiro Nishizawa

Hi,

I need to correct my answer before. The rising time is much larger than 600uS, almost won't change with VOUT change. Hope the results help you.

5VIN1VOUT1A

5VIN800mV5A

17VIN1VOUT1A

Vincent Zhang