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/PWRFAL、/LOWBAT、/INT pin at TPS65023

masa0301
Intellectual 960 points
Other Parts Discussed in Thread: TPS65023

0624.deley time_TPS65023.pptx

Hi

I have a question about TPS65023.

Question①
Regarding the /INl pin, before all channel converter's enable high this pin output is open?

Question②
If /INl output trigger is enable, how many seconds of deley time?

please check the attach file.

Question③
Regarding /PWRFAL、/LOWBAT、/INT, before reset of UVLO, this pin out put is open.This is correct?

Best regards,

masa

  • 0
    TI__Genius 16870 points

    Hi Masa, 

    1. If you are referring to the INT pin then, no, the INT will be LOW while all converters and LDOs are disabled.
    2. If you are referring to the INT pin then, the INT pin goes to High Z state with enable going from low to high. The delay is less than us. That being said, after about 180us, the INT pin will probably go from High Z to Low until the DCDC is within regulation limits. That time depends on the application voltages, currents and capacitances. 
      1. I recommend deglitching the INT signal for about 5ms or whatever your application takes to ramp up. 
    3. If you drop below UVLO, then the INT pin will be high Z but, if the pull up voltage is coming from the VIN or TPS65023 then the voltage will be some voltage below the designed set point. 
  • 0 in reply to Michael Green
    Intellectual 960 points

    Hi Michael

    Thank you for your reply!

    Best regards,

    masa

  • 0 in reply to Michael Green
    Prodigy 45 points

    I have a question about the INT pin timing that I am not sure got answered in this.

    Say the outputs of the TPS65023 are stable and the unit has been on for some time and one of the DCDCx outputs falls out of regulation. What is the response time of the INT pin? That is, how long after the DCDCx output falls out of regulation could it take for the INT pin to react (pull low)? Is this the "The delay is less than us." that you gave to Masa to answer question 2?

    Thank you.