Interfacing am335x to TPS65217C. slvu551 made several changes to Figure 5/table 5 when updating from rev g to rev h. There are several contradictions and within the document that I would like guidance on.
1. VDD_MPU is connected to DCDC3 in fig 5...to DCDC2 in table 5...Does it matter which?
2. SYS capacitance was changed from 22uF (rev g) to 2.2uF (rev h). Was this intended?
3. VDDS pins were changed from LS1 (rev g) to LDO1 (rev h). What was rationale for change? Is it ok to leave VDDS on LS1?
4. VIO in fig 5 shows connection to DCDC1...note 11 implies VIO should be connected to always on LDO1. Which is recommended?
5. fig 5 shows SCL, SDA, and nINT pulled up to DCDC1...note 13 states they should be pulled up to VDDSHV6.
6. nINT AM335x connection was changed from EXTINTn (rev g) to GMPC_WEN (rev h). Was this intended? What was rationale for change? Furthermore, GMPC_WEN is on VDDSHV1, so if this was intended, pull up in note 13 should probably be changed to VDDSHV1 for nINT.
Any help will be greatly appreciated.
Regards,
John
