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TPS65217 - output stops after momentary power failure

Hirotaka Matsumoto
Guru 27565 points
Other Parts Discussed in Thread: TPS65217

Hi all

Would you mind if we ask TPS65217?

TPS65217's output stops after momentary power failure.

<Summry>
1. 260ms momentary power failure
2. Tempory, VDD5V(AC pin) decreases, and TPS65217C turns off.(LDOx, DCDCx are 0V.) 
3. After returning of momentary power failure, DC5V is supplied to TPS65217C, however TPS65217C doesn't turn on.
    ->TPS65217C's V_SYS doesn't output.

We'd like to send more detailed imformation.
However it includes customer's confidential information.
So, could you let us know your E-mail address?
My e-mail address : matsumoto-h@clv.macnica.co.jp 

Kind regards,

Hirotaka Matsumoto

  • 0
    TI__Genius 10885 points
    It sounds like the system is operating without a battery, is this true?

    If so, there could be a residual voltage on the BAT pin interfering with the power-path.

    Does floating TS and placing a 1k pull-down on the BAT pin fix the behavior?
  • 0 in reply to Richard Solarski
    Guru 27565 points

    Richard san

    Thank you very much for your reply.
    It sounds like the system is operating without a battery, is this true?
    ->Yes, correct. Out customer system is operating without a battery.

    We let ouy customer place a 1k pull-down on the BAT pin.
    And, we will send you our customer's circumstance as the reference data using private message.
    (We added pull down1kohm on the circuit.)

    Kind regards,

    Hirotaka Matsumoto

  • 0 in reply to Hirotaka Matsumoto
    TI__Genius 10885 points
    Matsumoto-san,

    Thank you for the private message. To summarize, the input voltage is dropping below UVLO and recovering quickly within the 1s fault delay when the power-path is turned off. This is occasionally leading to an undetected wakeup event.

    One way to prevent this is to manually drop the UVLO detection level in the DEFUVLO register, though this only gives additional headroom for this condition and needs to be configured each time the PMIC is reset.

    Another method is to extend the fault timing so that the rising edge of AC is properly detected as a wakeup event.

    A third method may be to monitor the SYS rail with a reset circuit that asserts the push-button, which should kick the PMIC back into active mode after a fault.
  • 0 in reply to Richard Solarski
    Guru 27565 points

    Richard san

    Thank you for very kind your reply!

    We explain(persuade) that our customer try doing your methods.
    And we will feed back from our customer.

    Kind regards,

    Hirotaka Matsumoto

  • 0 in reply to Richard Solarski
    Prodigy 110 points
    Hi Richard,

    I've run into a similar issue re this thread. Could you please point me to how to change the fault timing? I couldn't find related information in the part's data sheet, although I could be missing it.

    Thanks,
  • 0 in reply to onechil
    TI__Genius 10885 points
    Hi Onechill,

    My description was unclear, there is no fault timing in the PMIC that can be extended.

    If possible, the UVLO event should be exaggerated to make the rising edge easier to detect. This may require discharging completely to zero or delaying when the rising edge initiates.

    Best Regards,
    Rick S.
  • 0 in reply to Richard Solarski
    Prodigy 110 points
    Hi Rick,

    Sounds good, and thanks for clarifying.