Hi,
In our custom build board, we are using Sitara AM3599 processor along with Power management IC (TPS65910A3A1RSL).
Initially we have not observed any issue with supplies but as part of testing we do load test on all the power supplies, then we identified issue (@ Max load) on PMIC power supply rails (VFB2&SW2-VDD2 and VFBIO&SW10-VIO).
As per the Datasheet the we should be able to load 1.5 A on VDD2 lines and 1 A on VIO line, but when we load the line for 1.5 (VDD2) and 1A (VIO) we have observed the drop in supply voltage.
After complete referring the data sheet of TPS65910A3A1RSL we understood that Max load of line can be configured through EEPROM register values.
We have read the REF_REG of line VIO and VDD2 and understood that lines have been configured for 0.5A with 1.5V for VIO and 1 A with 1.1V for VDD2.
Description (Address) |
Register values (Data Read) |
Data Supposed to be (for required load) |
VDD2 control register (0x24) |
0x05 (1.1V ,1A) |
0x25 (1.1V, 1.5A) |
VIO control register (0x20) |
0x01 (1.5V, 0.5A) |
0x04 (1.5V, 1A) |
We want the lines VIO and VDD2 to be configured permanently for max load possible , could you help us on this.