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TPS65910: TPS65910: TPS65910 start-up issue2

Kummi
Mastermind 6220 points
Part Number: TPS65910

Hello Kevin,TPS65910 team,

I am starting a new thread on same topic because the below post is Locked.
e2e.ti.com/.../585881

Could you please let me know if you have any updates on the TPS65910's VRTC LDO issue above.

In your earlier post you had mentioned that

"Next step from my side is to try to identify if there are special steps that need to be taken that may
not have been sufficiently documented to ensure that the processor does not draw more than 100 uA
until PMIC is out of NO SUPPLY state."

As we have reported many issues related to Startup(VRTC LDO) and also from your test,
it is evident that we need to provide a documented detail to the customer to be careful
when designing TPS65910(especially VRTC LDO).

Best Regards
Kummi

  • 0
    TI__Genius 17380 points

    Hi Kummi,

    The last action from the previous thread was to see if customer was using the PMIC VRTC for any of the pull-ups and if so, to disconnect them from PMIC VRTC to see if the issue was fixed.

    Were they able to check / perform these tests?

  • 0 in reply to Kevin LaRosa
    Mastermind 6220 points
    Hi Kevin,

    Thank you for the reply.

    I am sorry that I couldn't mention on the previous E2E that
    there are no pull-ups connected to the PMIC VRTC in this application.
    Actually our customer's schematics was reviewed by TPS65910 team.

    As I have posted in different E2E posts, we have more than 4 customers with
    4 different applications having similar issue with TPS65910's VRTC startup.
    Both A3A1 and A31A1 versions.

    It would be very helpful for new customers using TPS65910, if there is some
    details on this limitation in the manual or wiki.

    Best Regards
    Kummi
  • 0 in reply to Kummi
    TI__Genius 17380 points
    Hi Kummi,

    I've just submitted a document update request to add a note to the user guide that VRTC defaults to the low-power mode and that load must stay below 1 mA prior to boot to ensure that VRTC is able to reach 1.8V and allow OTP to load.
  • 0 in reply to Kevin LaRosa
    Mastermind 6220 points

    Hi Kevin,

    Thank you very much for updating the User guide.
    We appreciate your support.


    There is some confusion with the statement on the user guide(SWCU093F).
    The note in the user guide mentions that "If the current load exceeds 1 mA".

    But, as you know our previous discussion on different E2E posts were about 100uA(0.1mA).

    You have mentioned before that,
    Next step from my side is to try to identify if there are special steps that need to be taken that may not have been sufficiently
    documented to ensure that the processor does not draw more than 100 uA until PMIC is out of NO SUPPLY state.

    Could you please clarify about this.
    Actually we have mentioned to all our customers about 0.1mA and also TPS65910 datasheet mentions
    that Back-UP current as 0.1mA, so we could relate this issue with datasheet value also.

    One more thing is, with regards to this limitation mentioned in the user guide,
    what could be the possible way to avoid current load to VRTC LDO?
    Will it be OK if we design the circuit as per the Figure 1 and Figure 2 mentioned in the user guide?

    Best Regards
    Kummi

  • 0 in reply to Kummi
    TI__Genius 17380 points

    Hi Kummi,

    Thank you for the follow up, I am misread my previous E2E post and mistakenly put 1 mA instead of 0.1 mA. While 1 mA was the current I was able to supply on the one unit I tested on the EVM, the specification in the datasheet is 0.1 mA so I should have written 0.1 mA instead.

    I should have this updated in the next couple days, my apologies for the error.

    It still isn't clear why Figure 2 setup is not working for these customers. I was revisiting this post because it is roughly the same; did we ever have your customers try enabling the processor RTC by setting RTC_KALDO_ENn and disconnecting CAP_VDD_RTC?