Hi,
We got a question from the customer about TPS43350-Q1.
Could you help us?
[Question]
- Is there a prot of Current Limit vs Duty Cycle characteristics at Vin=10V and Vin=16V
- How much is the variation of Vsense at each duty cycle? According to datasheet, the variation is +/-20% at low duty cycle. They want to know it at high duty cycle.
Their condition includes high duty cycle. So they need these information.
Vin=10 to 16V
Vout=8V
Iout=2A
Best Regards,
tateo
Hello Tateo,
as Brian suggested, we do not have explicit data for 16V.
The part will limit the current at 75mV (minus slope compensation), which provides the protection you asked for.
Customers have to design with margin.Here, they will need to consider the tolerance and chose a resistor that is rather too small, to avoid current limit at a too low level, but choose the other other components so that they can conduct the worst case (highest) current until the current limit will kick in.
See also example in datasheet:
We provide a calculation tool that aides the component selection (but is intended as a starting point, and will need to be evaluated in customers design):
TPS4333x-Q1, TPS4335x-Q1 Switching-Mode Power-Supply Component Calculation Tool
Best regards,
Frank
Hi, Thank you for your support. They measured the current limit on EVM Vout B. Please refer to below plots. They want to make sure about the behavior of the current limit. Could you confirm these questions?
1. Which points in this plots does the IC start the behavior of current limit(Vsense/Rsense)?
2. Why does the current increase as the output voltage decreases?
3. Is this the behavior of current limit with foldback?
Best Regards,
tateo
Hi, Sorry to bother you again. They measured the load current by their own board. So they found the big variation of current limit between 2 board. We understand to have to estimate 25% variation of Vsense. But could you confirm these questions?
- They measured comp voltage at each boards. It seems the IC starts the behavior of current limit when comp voltage reaches about 1.55V clamp voltage. Are there any relationship between comp voltage and Vsense?
- If comp voltage is related to Vsense, they want to prevent the variation of comp voltage. Are there any solution for this?
- They think there is big variation even though they measured only 2 boards. Do you think this is typical performance of the IC?
Best Regards,
tateo
Tateo-san,
Yes, there is indeed a relation between Vsense and COMP, see datasheet page 11, Figure 6:
This also explains the clamping at ~1.55V.
This is part of the current mode architecture and can not be changed!
The variance in current limit indeed looks rather large, I suggest they double-check the values and connection (incl solder joints) of their sense resitors. Also, please have them check their current-rating for th einductor: if the inductor is driven into saturation, the ripple will significantly increase and may lead to a peak-limit at a lower average current. It would be helpful to take a graph showing Vout, Comp and inductor current (idelaly via a current-probe attached to a wire-loop from the inductor to R-sense). Alternatively, a differential measurement across the sense-resistors would do, but those may compomize the behavior of the sense-resistor due to added capacitance and - in case of a inaccurate value or connection of the sense-resitors - the calculated current would also be wrong...
The graph in your previous query needs some explanation:
Can you please let me know in which scenario this data was taken? I assume the part was powered up (i.e. VBAT is turened on, while the rail is already enabled)? Or has VBAT been present abd then EN was pulled high?
The initial slope on Vout may be just following VBAT, while the softstart kicks in for the 2nd part of the slope with a large inruch current in between. If not already done, please request a plot with VBAT being available before the rail is enabled.
Best regards,
Frank
Hi, Thank you for your support. I confirmed the following from them.
- They checked the value and connection of Rsense, and it should be ok. But they are using Rsense in 3 parallel. So they will try to measure by single resistor.
- They are using 3.7A rating inductor. We are sure it is enough for their condition.
- All plots is measured in the condition which VBAT has been present and then EN was pulled high. The Load is CR mode by electronic load.
- I simulated a relation between comp voltage and load current. It seems comp voltage increases as the load current increases. Please refer to attached file.
TPS43350Q1 PSPICE_16JAN18.pptx
They want to make sure the factor to vary the current limit. They assume one of the factor is comp voltage. Could you confirm whether the variation of current limit is related to comp voltage, or not?
Best Regards,
tateo
Tateo-san,
thanks for sharing the further details.
As previously said, the COMP voltage is indeed directly related to the VSENSE-voltage and this ratio can not be altered. I noticed that the graph I inserted does not show here, so in case this happens again, please refer directly to the TPS43350-Q1-datasheet, page 11, Figure 6:
In order to change the current limit, the the current-sense-resistor needs to be changed. However, when doing so, please be aware that the inductor and conesequently the output filter and compensation need to be adapted as well (see Section 8 in datasheet).
The clamping will always happen at ~75mV peak sense voltage, corresponding to a COMP-voltage of ~1.55V.
I took a look at the chosen components, assuming the screen-capture with "8V, 2.2A peak" is correct:
Due to the high duty-cycle for 8V output, the peak sense voltage should be in the order of 45mV (see the graph in your original request, i.e. datasheet Figure 10) and reducing this value by 25% to leave some margin, the sense-resistance and inductor are chose appropriately for 2.2A peak. (your simulation is using 5V output,so it is not representative for 8V and associated loads).
However, the compensation is a little odd: the resistance sets a unity-gain-bandwidth of ~73kHz, on the agressive side, but within limits. However, the series capacitor (47nF) is way too high, setting the zero-frequncy to ~300Hz, while it should be in th order of 7kHz. I suggest to use ~1.8nF. The parallel capacitor is correctly chosen with ~47pF, setting the 2nd pole to ~280kHz.
I suggest to adjust the compensation.
Note, these calculations do take some assumptions (e.g. about output capacitors ESR) and do not take any parasitics into account. It's customers responsibility to validate this in his design across use-case conditions.
