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Delay time of Power-Management Sequencing on TPS65950

Other Parts Discussed in Thread: TPS65950, AM3715

We are using TPS65950 and AM3715 on our device installing WIndows CE.

We are reviewing "sleep on" and "sleep off" sequence of our BSP.

However, we don't know whether delay words on Power-Management sequence are correct or not.

How do we decide the value of these daly words.

For example, Active to sleep sequence is as following.

    step1: MSG=0x00f0 Delay=0x04  : VDD1->WAIT-ON and delay 4*31.25us=125us

    step2: MSG=0x0100 Delay=0x02 : VDD2->WAIT-ON and delay 2*31.25us=62.5us

    step3: MSG=0x0070 Delay=0x03 : VPLL1->WAIT-ON and delay 3*31.25us=93.8us

    step4: MSG=0x0190 Delay=0x03:  HFCLKOUT->WAIT-ON and delay 3*31.25us=93.8us

        VDD1 is connected to vdd_mpu_iva.

        VDD2 is connected to vdd_core.

        VPLL1 is connected to vdda_dpll_per and vdda_dplls_dll.

        HFCLKOUT is connected to sys_xtalin.

Should we concern with the stable time for vdd_mpu_iva, vdd_core, and so on?

If so, where is the stable time written?

We don't know whether 125us, 62.5us, and 93.8us is correct or not.

And we don't know how these values are decided.

 Please let me know.