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TPS2375-1 Reference Design

Gergely Bacso
Intellectual 545 points
Other Parts Discussed in Thread: TPS2375EVM

Hi,

I have let the reference design found in www.ti.com/.../tps2375-1.pdf (page 1) made as part of a PoE application. Triple-checked everything, but this part doesn't work.

Even the detection phase goes wrong: when I manually begin to add voltage between the "~" pins of any of the two bridge rectificiers, the circuit begins to consume a lot of current (10mA @ 2V and 0.5A @ 2.7V and exponentially growing (didn't dare to go above 1A)).

Does anyone have an idea, what could go wrong?

Thanks,
Gergely

  • 0
    TI__Mastermind 40530 points
    Hi Gergely,
    I would start off by looking for shorts on the board. Can you try bypassing the the diode brdige and placing the power between VDD and VSS?
    Lastly, I would order and EVM and start comparing impedances. It sounds like there might be something shorted or possibly wrong assembly on the board that could be the issue.
  • 0 in reply to Darwin Fernandez
    Intellectual 545 points
    Hi Darwin,

    I checked every pin with every pin twice in this section, and no shorts, no tears. Everything physically seems as in the schematic. Placing power directly between VDD and VSS gave the same bad results. I'm beginning to think that there is something wrong with the TPS2375PW-1.

    I think I will try a TPS2375PW (Latch) as in the EVM. Or is there an EVM with TPS2375PW-1 (Auto Retry)?
  • 0 in reply to Gergely Bacso
    TI__Mastermind 40530 points
    Hi Gergely,
    There not a -1 EVM. However, the TPS2375EVM can accomodate the -1's PW package for your testing.
  • 0 in reply to Darwin Fernandez
    Intellectual 545 points

    Hi Darwin,

    thank you for your answer, and fast response.

    Before buying an EVM, I tried assembling this circuit part by part on a clean PCB, and it turned out, that the rectificiers were with wrong polarity.

    It works now well, except that between VDD and RTN there is 56.3V, which was unexpected for me: I expected there the UVLO limits (30.5V - 39.3V). I'm not a professional in analog electronics, did I misunderstand something?

    Can you tell me the upper and lower voltage limits between VDD and RTN for TPS2375PW-1?

    Thank you,
    Gergely

  • 0 in reply to Gergely Bacso
    TI__Mastermind 40530 points

    Hi Gergely,

    The IC enables the output (VDD-RTN) when when the input PoE voltage (VDD-VSS) is above UVLO_HIGH (39.3V) and shuts down the output when the input goes below UVLO_LOW 30.5V.

    The output should be very close to your input voltage (minus the RDSon drop of the internal FET). IEEE standard requires a voltage range of 37-57V to be compliant.

    There is no over voltage protection or voltage limiter within the IC itself. The SMAJ58A helps clamp the input during transient events but that's about it. This means that the input voltage should not go above its abs max rating of 100V (recommended is 57V max for normal operation).

  • 0 in reply to Darwin Fernandez
    Intellectual 545 points

    Hi Darwin,

    thank you very much for your help. Everything is clear now.

    Gergely