LM5060-Q1 Design Questions

Hi Tateo,

I will get back to you tomorrow with initial feedback. We do not have all of these answers on hand, but will address those we can.

Thanks,
Alex

Hi Tateo,

Comments:

What is the purpose of changing Itimerl(6uA) to Itimerh(11uA) in start up time?

         - This serves to set a "start up time". During normal operation, it should take a certain amount of time for the device to power on and produce 5V of Vgs voltage. When powering on, the Vds across the MOSFET is large, and so without a startup timer, the LM5060 would not know whether there is a fault during startup or not. Having this "one shot" clear of the TIMER cap after Vgs = 5V serves to distinguish startup from an actual fault.

          - If Vgs never reaches 5V, then there must be a fault and so the system would shut off.

- Is there any shutdown sequencing requirement?

          - No, you can shut down from EN, UV, OV, VIN POR in any order.

- How much is the value of EN pin input impedance?

          - I'm not sure and this may be difficult to find out since it is not characterized within the EC table. What are the customer's concerns regarding EN?

- Could you tell us the internal charge pump circuit and fsw of charge pump?

           - I don't have the exact value but it should be in MHz. The node is high impedance, there should be minimal ripple or noise.

 My customer consider VIN bypass capacitor.

 He want to know about frequency of ripple and noise from chrge pump circuit.

- In reverse current event, my customer should care of OUT pin and SENSE pin reverse current limit.

 Datasheet show us OUT pin reverse current is 4mA max and SENSE pin reverse current is 25mA.

 Is these value's condition including over temperature?

             - This will be difficult to find out, since this is a device from National Semiconductor and this test information is not part of the standard characterization data. Overall, the reverse current ratings are meant to limit the current (and therefore voltage) through the ESD protection diodes on the pins. Figure 34 uses external protection diodes which will limit the voltage across these pins to below the maximum ratings. Figure 38 uses resistors to limit the current through these pins to below the maximum ratings.

- Datasheet recommend Figure 34 at if the output load is highly capacitive.

 Why does the D5 and D7 is needed to protect internal diode? What is the path of this current flow?

            - Yes, the internal diodes are not for high power. Additionally, there are internal ESD protection didoes from GND to the pins. So in the reverse input voltage test, current will flow from GND to OUT and then through D7 to SENSE, then through R12 to INPUT. Unfortunately, we do not have the original, documented test results for either Figure 34 or Figure 38. A few months ago, I built up Figure 38 to create documented test results, see the presentation attached at the bottom. As a result, we would recommend Figure 38 vs Figure 34 as it is simpler (use resistors on all the pins to limit the current) and we have some recorded test results.

- The OUT pin reverse current limit is 25mA. Why is 25mA?

 What does the internal circuit be related?

 And in figure 34, what do you recommend If-Vf characteristic of D5?

          - We recommend to limit the reverse current less than 25mA in order to protect the internal ESD diode from GND to OUT. Having a 10k resistor such as in Figure 38 would be sufficient to limit this current.

- In figure 34, how is the method of R1 protect the GATE pin from reverse current exceeding 25mA?

See the attached presentation regarding the D4 + R1 circuit on the GATE and the effects of having D4 or not.

2022.LM5060 Reverse Polarity Protection.pdf

Thanks!

Alex

Thank you for your help. My customer has more questions. Could you help us?

 - My customer has question from data sheet Figure 22. "Voltage During Normal Start Up Sequence".
   What is transition region? He is thinking Vgs is ramp up riniarity 0V to Vth.
   Why does it have 2 stage of Vgs charging?

 - My customer concerns about EN pin voltage drop. He considers to input to EN pin from MUC.
   He should use series resistor. So he is worried about EN pin voltage drop.
   He need EN pin input impedance. Could you tell us it?

 - My customer has question about Figure 34. .

    #If the output load is highly capacitive, datasheet recommend Figure 34. .
     What is the special function of Figure 34?

    #What is the path of D5 and D7 current flow in the reverse polarity situation?

    #D5 protects the internal zener diode in the event o reverse input polarity.
     He is thinking Vf of D5 should be lower than Vf of internal zener diode.
     What do you recommend If-Vf characteristic of D5?

    #The resistor R1 protects the GATE pin from reverse currents exceeding 25 mA in the reverse polarity situation.
     What is the path of R1 current flow?

 - My customer considers low input voltage operation. So he considers UVLO is disable. And he is only use POR.
   Is there any problem of this operation?
   How is the processing method in the case of UVLO pin non-use?

 - Could you tell us POR characteristics?
    PORen: Could you tell us minimum value?
    PORen-his: Could you tell us minimum and maximum value?

 - If EN is Low, what is the condition of each pin? (High-Z, GND, xxkohm, etc)

 - Could you tell us TIMER pin characteristics?
    Vtmrh: Could you tell us minimum and maximum value?
    Vtmrl: Could you tell us minimum and maximum value?

Best regards,
tateo

Hi Tateo,

Unfortunately we do not have documented test results, nor original characterization data for the LM5060 which makes these questions difficult to answer. We plan to release a tested, reverse polarity solution for the LM5060 in the future but that project has not begun yet.

Having said that, we have done a lot of testing with the LM5060 in our lab and can answer many of the questions you had asked. See comments below.

- My customer has question from data sheet Figure 22. "Voltage During Normal Start Up Sequence".    What is transition region? He is thinking Vgs is ramp up riniarity 0V to Vth.    Why does it have 2 stage of Vgs charging?

During startup, the GATE will charge with a sourcing current of 24uA. Once the FET begins to conduct (reaches Vth), then both the Vgate and Vout will continue to rise in unison. So the voltage difference will be roughly constant (the Vth of the MOSFET) and in this picture, that is the "transition region". Then once the output voltage is up to VIN, then the GATE will continue to charge and eventually reach 5V Vgs (which is called "Vgate-th" in the datasheet), which is the point where it discharges the TIMER.

- My customer concerns about EN pin voltage drop. He considers to input to EN pin from MUC.    He should use series resistor. So he is worried about EN pin voltage drop.    He need EN pin input impedance. Could you tell us it?

The pin is high impedance and works up to high voltage. There is a 6uA (typ) bias current, so the resistor should be sized appropriately in order to supply at least 10uA of current. Overall, a 1k or 10k in series should be sufficient.

- My customer has question about Figure 34. .

    #If the output load is highly capacitive, datasheet recommend Figure 34. .      What is the special function of Figure 34?

This circuit was developed and tested by National Semiconductor. The original test results were lost during the aquisition. We do not have this information.

    #What is the path of D5 and D7 current flow in the reverse polarity situation?

    #D5 protects the internal zener diode in the event o reverse input polarity.      He is thinking Vf of D5 should be lower than Vf of internal zener diode.      What do you recommend If-Vf characteristic of D5?

Yes, D5 Vf should be lower than internal zener diode Vf. Overall, we know the original circuit was tested with 40V, 1A SOD123F size schottky diode. We do not have part numbers.

    #The resistor R1 protects the GATE pin from reverse currents exceeding 25 mA in the reverse polarity situation.      What is the path of R1 current flow?

Q3 becomes activated in a reverse polarity condition. My initial analysis is that this can cause a current path from GND to GATE (through internal ESD diode protection) then through R1, through Q3, through Q1's body diode, and to VIN.

- My customer considers low input voltage operation. So he considers UVLO is disable. And he is only use POR.    Is there any problem of this operation?    How is the processing method in the case of UVLO pin non-use?

This is perfectly fine, just keep in mind that POR may cause the device to shut off at 5.46V (max)

- Could you tell us POR characteristics?     PORen: Could you tell us minimum value?     PORen-his: Could you tell us minimum and maximum value?

We do not have this information.

- If EN is Low, what is the condition of each pin? (High-Z, GND, xxkohm, etc)

You can see from the block diagram on page 10) of the datasheet. If EN goes low, this would activate a 2.2mA pull down current on the GATE and disconnect the bias circuitry. Input current would drop to 9uA typical. The OUT will drain 2.2mA through the internal zener diode, then through the GATE's 2.2mA pull down.

- Could you tell us TIMER pin characteristics?     Vtmrh: Could you tell us minimum and maximum value?     Vtmrl: Could you tell us minimum and maximum value?

We understand this is an important parameter, but unfortunately we do not have this information.

Thanks,

Alex

Thanks again. Can I confirm these question?

 - I have question about Figure22. . In your explain, is it different Vth and Vgate-th?
   Do you mean that Vth is MOFET Gate cut off voltage and Vgate-th is LM5060 characteristic?

 - When EN is Low, what is the path of the Gate to OUT current folow? Is this figure correct?

Best regards,
tateo

Hi Tateo,

1) Yes, that is the gate cutoff voltage and Vgate-th is the LM5060's characteristic.

2) When EN is low (the device is disabled), then the 2.2mA gate pull down current is activated. This will sink the 24uA from the gate charge pump, drain the MOSFET's gate capacitance, and drain the output capacitors through the following path:

Also note that current will go from OUT through the 1kohm resistor, through the Vds fault comparator diode, through the 500ohm resistor and to SENSE pin (see description "Reverse Polarity Protection with a Resistor" on page 24 of the datasheet, along with Figure 35).

Thanks!

Alex

Thank you for your help. My customer is evaluating LM5060-Q1 on EVM. He has ploblem.

 - Ploblem -
  When LM5060-Q1 is over current event, FET is over SOA maximum rating.
  My customer considers method of shorten the over current event time.
  So he has an idea that is reduce the TIMER pin capacitor value.
  Now the schematic is under the below.

 - Question -
  # Is there other method of shorten the over current event time?

  # If he reduce the TIMER pin capacitor value, start up time become fast.
    So TIMER pin characteristics become very important.
    Is there no way to get the variation of VTMRH and VTMRL at over Tj?

  # VDS comp has 1k ohm and 500 ohm. Does the SENSE pin Voffset include of the variation of 1k ohm and 500 ohm?
    Should he consider the variation of 1k ohm and 500 ohm?

Best regards,
tateo

Hi Tateo,

I'm discussing with my team on what we can do about the TIMER threshold values over temperature. We're digging through all the files again to see if we can find these values.

How did your customer perform the overcurrent event testing? Note that the LM5060 is meant for very gradual overcurrent events (where the Vds across the MOSFET is very small), which would remain within the MOSFET SOA. If it is a stronger overcurrent event (where Vds across the MOSFET becomes large), then the LM5060 may not be able to protect the MOSFET. This is because the LM5060 does not have active current/power limiting and relies on the MOSFET's Rds-on (which varies greatly over temperature) for it to understand what the current value is.

Instead, we offer devices such as the LM5069 which have active current limiting (will regulate the GATE voltage to keep current below a threshold), and active power limiting (regulates the GATE to keep the MOSFET power dissipation below a certain value, in order to protect the MOSFET within its SOA). Lastly, the LM5069 offers a circuit breaker shutdown, where it will perform a fast gate shut down if current exceeds the current limit by 2x (such as from a short circuit).

We also have application notes and EVMs (with documented test results) for the LM5069 for reverse input polarity solutions.

What temperature range is your customer's application. We assume AEC-Q100 compliance is required, but would Q100, Grade 2 temperature testing be sufficient (-40C to 105C), or do they need Grade 1 (-40C to 125C)?

Thanks!

Alex

I discused with my customer. My customer understood the problem is power Loss at gate turn off.
So he will try to remove gate capacitor.

And thank you for your suggestion. I think LM5069 is better.
I have confirmed the temperature requirment. He need Grade 1 (-40C to 125C).
But I have one concern. It is input voltage range(+9 to +80V). I will confirm from my customer.

Best regards,
tateo

Hi Tateo,

 

The LM5060 is the only Q100 Grade 1 hot swap device we have.

 

Thanks,

Alex

Hi Tateo,

We are working hard to get this data. We are digging through, sorting, compiling and analyzing all the raw characterization data to get as many of these parameters as possible. We will have the TIMER pin and PG min/max value spec by the end of this week. Revising the datasheet will take some time, but is scheduled by the end of this year.

Thanks!
Alex

Thank you for your support!
I would appreciate your continuous support.

And let me know what is PG min/max? Is it PORen?

Best Regards
tateo

We'd very much appreciate your kind support.
I'll check the data.

Best Regards,
tateo