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TPS24712 / About FLT pin signal.

Sho Ogane
Genius 5575 points
Other Parts Discussed in Thread: TPS24712, LM5069

Hi all.

Do you guarantee that FLT pin output is Low when TPS24712 is "power on" or "power off"?

I concern when this device is power on or power off, FLT pin output is High.
I don't expect that output is High.

Best Regards,
Sho


  • 0
    TI__Expert 5940 points
    Sho

    Upon Power Up and Power Down, FLT (and FLTb) and PG in the TPS247xx series have a known glitch. It has to do with device initialization upon application or removal of power. The glitch = ~ 4 usec duration and typically is within the 1st (20-30)usec of application of EN. TI recommends that FLT be ignored by the system for the 1st 300usec of power up and ignored upon EN/ENSD deassert for power down .

    Brian
  • 0
    TI__Genius 12420 points
    Hi Sho,

    To add to Brian's message, you can also add an RC delay for filtering if desired. Check out the LM5069 datasheet Figure 37 for ideas on different RC delays depending on rising edge only delay, falling edge only delay, or both:
    www.ti.com/.../lm5069.pdf

    Thanks,
    Alex
  • 0 in reply to Alex Triano
    Genius 5575 points

    Hi Brian san, Alex san.

    Thank you for your great supprt.

    I have one more question about Brian san's message.
    This is your comment,
    "TI recommends that FLT be ignored by the system for the 1st 300usec of power up"

    ・Question
    Is it better to ignore 300usec after being supplied stable power?
    Or after starting supply power?

    Best Regards,
    Sho

  • 0 in reply to Sho Ogane
    TI__Expert 5940 points
    Sho,

    300usec is timed from either Vin or ENSD reaching valid levels. ENSD (1.4v), Vin (2.45v). In cases where Vin rise is slow (Vin softstart without hotswap insertion), Vin rise can be in the 10's of msec. If your system monitors Vin or Vout, then this can be done from this monitoring. If your system apples ENSD after Vin has been applied, then the 300usec 'ignore' period begins from ENSD reaching 1.4v. The RC filter Alex guided you to will effectively 'deglitch' PG and FLT outputs as long as the RC timing masks into the circuit it feeds (RC slope to the voltage it recognizes for the logic transition). The glitch could be up to 10usec in duration (our lab measurements are ~ 4usec). Best to have tolernaces push this to 25usec or more deglitch for margin.

    The best overall solution would be for the end system to ignore PG/FLB signals digitally for 25usec (or more) all the time and the 300usec wait period isn't needed.

    Brian
  • 0 in reply to Brian Daugherty
    Genius 5575 points

    Hi Brian san, Alex san

    Thank you for your support.

    I understood that I need to ignore 300ms from Vin reaching valid level.

    By the way, I recommended RC filter.
    I am asked from my customer the recommended R and C value.
    Please tell me the value.

    Best Regards,
    Sho

  • 0 in reply to Sho Ogane
    Genius 5575 points

    Hi Brian san, Alex san

    How about my question about RC filter value?

    I am waiting your comment.
    I would like to get it as soon as possible.

    Best Regard,
    Sho

  • 0 in reply to Sho Ogane
    TI__Expert 5940 points
    Sho,

    FLB is an open drain output and will be pulled up to a system voltage with a resistor. The voltage on FLB will rise per:

    Vrise = (Vpull up)* {1 - e^(-t/RC)}

    So you need to assure that the RC keeps 'Vrise' from reaching the minimum threshold point of what ever this line feeds (with margin). So you need to know the pull up voltage and the downstream device's minimum threshold for a 'high' signal. For instance, if the pull up is 3v, and the minimum threshold = 1.5v, then an RC (tau) of 7.21usec will allow 1.5v to be reached in 5usec, which is the duration of the glitch. Recommended margin to prevent a trip in the end system would be ~ 50usec TC (about 7x). So R = 22.6k, C = 2200pF. But again, this depends on the pull up voltage and what is recognized as a high by the system. Don't go too large on the capacitor as it will discharge into the TPS24712 transistor. A small resistor (100 ohm) as shown in the middle diagram of the LM5069 fig 37 will limit peak current back into the FLT pin and prevent any possibility of damage to the pin.

    Brian