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PTN78000HAH

Eric Strohbehn
Intellectual 360 points

The requirement for output capacitor ESR is confusing us.  This is on page 14 of the datasheet.  It says the ESR for the electrolytic capacitors can be no lower than 10 mohms (17 m ohms for a single electrolytic capacitor).  However, the following paragraph says the ESR is not critical for ceramic capacitors.  This is causing our analog experts to still apply the ESR limit to the ceramic capacitors since they say capacitance is capacitance and ESR is ESR whether it is electrolytic or ceramic.  But we need more ceramic capacitors for the loads we have.  So we are between a rock and a hard place and can't agree how to use the PTN78000HAH.

So why the ESR limit on the electrolytic capacitors when you place no ESR limit on the ceramic capacitors?

Eric

 

  • 0
    TI__Mastermind 38230 points

    PTN78000Wxx and Hxx  require a minimum 100µF output polarized capacitor with ESR ≥17mΩ total fro polarized capacitors.

    .Ceramic output capacitance  including  the minimum 100µF polarized capacitor  has ceramic capacitance limited to maximum  200µF regardless of total ceramic capacitance ESR which is typically <5mΩ. In the product PTN78000Hxx specification .

    Tom

      

  • 0 in reply to Tom Guerin
    Intellectual 360 points

    Tom,

    Your answer is a reiteration of what the datasheet says.  This does not help us resolve our problem.  Our problem is that for all other regulators we have seen the ESD limit was for total capacitance to limit the current surge during power up.  If the intent is to limit the current surge you can't do that by relaxing the requirement for the ceramic capacitors.  The surging into the ceramic capacitors will be just as much a problem as surging into an electrolytic capacitor.  So our analog experts don't understand the requirement and this is making the board design very difficult.  What problem are you fixing with this ESR requirement?

    Eric

  • 0 in reply to Eric Strohbehn
    TI__Mastermind 38230 points

    Eric:

    The capacitor limits are published  for maximum stability of the power module.

    I recommend you send me an e-mAIl so we can discuss this question off line.

    tguerin@ti.com