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Is it importment to choose the MOSFET for LM3150?

Jacking Jin
Expert 1145 points
Other Parts Discussed in Thread: LM3150

Dear,

At present, I used the LM3150 to design a buck converter, the chip is very hot at no load, when with  load will more hot.

The SCH is according the reference circuit of the datasheet. I had test all pin signal are normally. Idon't konw why happened this case.

In the case, I have changed the MOSFET, the chip become better, the biggest different is Qg of the MOSFET.

So I want to know whether the MOSFET's Qg is importment character for the chip.

  • 0
    TI__Guru**** 191445 points
    Moving to the simple switcher forum...
  • 0
    TI__Genius 11085 points

    The LM3150 provides gate drives to the external FETs. Yes, the Qg of the FETs determines how much drive current the LM3150 has to provide.

    There's a guide line on the datasheet page 17, please check with your design:

    7. MOSFET and RLIM Selection

    The LM3150 controller is designed to drive N-channel MOSFETs. For a maximum input voltage of 24 V we

    should choose N-channel MOSFETs with a maximum drain-source voltage, VDS, greater than 1.2 x 24 V =

    28.8 V. FETs with maximum VDS of 30 V will be the first option. The combined total gate charge Qgtotal of the

    high-side and low-side FET should satisfy the following:

    Qgtotal ≤ IVCCL / fs (48)

    Qgtotal ≤ 65 mA / 500 kHz (49)

    Qgtotal ≤ 130 nC (50)

    Where IVCCL is the minimum current limit of VCC, over the temperature range, specified in the Electrical

    Characteristics table. The MOSFET gate charge Qg is gathered from reading the VGS vs Qg curve of the

    MOSFET datasheet at the VGS = 5 V for the high-side, M1, MOSFET and VGS = 6 V for the low-side, M2,

    MOSFET.

    Regards,

    Yang

  • 0
    TI__Expert 6860 points
    Hi Jacking ,

    Can also please share your Layout for the design . I am interested to see how the exposed Powerpad underneath the IC is connected .

    With Best Regards
    Ambreesh
  • 0 in reply to Ambreesh Tripathi
    Expert 1145 points

    Dear Ambreesh,

    The layout as below of the design, the FB line is a little long. Please kindly give me some suggestion for the Layout, many thanks!

  • 0 in reply to Jacking Jin
    TI__Expert 6860 points

    Hi Jacking,

    In the buck converter,  HF bypassing of the input/output containing the pulsing current is very important. Most attention needs to be paid to the return path from the LS FET ground to the ground node of the bypass cap.THis will minimize the critcial di/dt loop area .

    In the design , you can see how big tha loop is :

    I would recommend you to follow the layout if the EVM :

    http://www.ti.com/lit/ug/snva371d/snva371d.pdf

    Further as far as FB components are concerned , it should alway be placed away from switch nose and closer to FB pins . Longer FB trace wont have any issues and your implemeation is alright for the feedback node  .

    With  Best Regards

    Ambreesh

  • 0 in reply to Ambreesh Tripathi
    Expert 1145 points

    Dear Ambreesh,

    OK. Thanks for your support, many thanks!