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TPS3851: TPS3851 / Timeout-counter is reset when SET1 pin to Low?

Part Number: TPS3851

Hi,

I understand that the watchdog timer is disabled when ISET1 pin is grounded. Then does it mean that timeout-counter is also reset?

Best Regards,

Satoshi / Japan Disty

  • Satoshi,

    Please explain your question. /RESET only depends on VDD and /MR. If watchdog is disabled, this means input to WDI is ignored.

    -Michael
  • In reply to Michael DeSando1:

    Hi Michael,

    I'm asking just simple question. Is the internal counter reset when SET1 is changed from High to Low as attached?

    Best Regards,

    Satoshi

  • In reply to S.Satoshi:

    Satoshi,

    No. SET1 has no impact on the internal counter. The SET1 connects to an internal state machine which uses logic to disable the /WDO. The internal counter doesn't depend on SET1. When SET1 goes high and enables the watchdog, a 150-us setup time reinitializes the watchdog before checking any inputs on WDI.

    Does this answer your question?

    -Michael

  • In reply to Michael DeSando1:

    Hi Michael,

    Thank you for your point. Let me ask one more question to clarify my understanding.

    I understand that tWD is started at this point and also started to check WDI input (See attached). Is my understanding correct?

    Best Regards,

    Satoshi

  • In reply to S.Satoshi:

    Satoshi,

    Your text in blue is correct. Please let me know if you have any more questions. Thank you!

    -Michael

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