Other Parts Discussed in Thread: , TPS3850
Hello
I am considerung to use the TPS3851 or 3850 but am confused about the WDO functionality. In both datasheets this is written:
"The TPS3851-Q1 features a watchdog timer with an independent watchdog output (WDO). The independent
watchdog output provides the flexibility to flag a fault in the watchdog timing without performing an entire system
reset. When RESET is not asserted (high), the WDO signal maintains normal operation. When asserted, WDO
remains low for tRST. When the RESET signal is asserted (low), the WDO pin goes to a high-impedance state.
When RESET is unasserted, the watchdog timer resumes normal operation."
I don't understand why it's mentioned twice when RESET is asserted but has 2 different facts.
When I look at the block diagram I also don't understand how this exactly works. As I understand it is that if RESET Output is HIGH then the gate of its output FET is LOW. This LOW signal goes to the NAND gate of the WDO circuit. So we got a LOW signal on the NAND and whatever comes from the state machine. We will always get a HIGH at the output of the NAND gate, as long as the RESET FET gate is LOW. So we get a HIGH at the WDO FET Gate and thus we get WDO is LOW (active) although maybe the WDI signal is working correctly.
Do I missunderstand somethign or is there an error in description or in the block diagram?
Thank you for clearing this up.
Michel
