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TPS3808: CT Pin DC level

Steve Widener
Genius 9965 points
Part Number: TPS3808

If the CT pin on the TPS3808 is tied to 1/2 the supply rail (that would be 1.65V in the case of Vdd = 3.3V) would the device interpret that as being pulled to Vdd and subsequently provide a 300msec delay?

  • 0
    TI__Genius 12630 points
    Steve,

    Good question! I know the CT pin charges to a reference voltage of 1.23V. So I believe that if the CT pin is connected to any voltage via a pull up resistor so that the voltage at the CT pin reads above 1.23V, the device will think the CT pin is connected to VDD so it will provide the fixed delay of 300ms.

    I haven't confirmed the max CT pin current when using a pull-up resistor to VDD or some other voltage but if we assume the 220nA current that is provided by the internal current source when CT is open, and we assume the minimum pull-up resistance allowed (10k ohm) then we can see:

    1.65V is the pull-up voltage
    220 nA is the CT pin current
    10k ohm is the minimum pull-up resistance

    1.65V - Voltage drop across pull-up resistor = 1.65V - (10 kohm * 220 nA) = 1.65V - 0.0022V = 1.6478V

    Since this 1.6478V at the CT pin is greater than the internal reference voltage of 1.23V, I believe the device will think the CT pin is connected to VDD and will implement the fixed 300 ms delay.

    Please let me know if you have any additional questions or if anything I said is unclear or incorrect. Thanks!

    -Michael
  • 0 in reply to Michael_DeSando
    TI__Genius 9965 points
    Michael -

    Thank you for the prompt reply - we need some more information:

    1. I believe the 220nA charging current would be a high-side current mirror with a volt or so of compliance. That would make it look like a pull-up instead of a pull-down as described - correct? If so, how does that impact your calculations?
    2. Since the circuit provides 300msec delay when CT is tied high but 20msec when it is left open, I suspect there is more going on than the comparison to 1.23V - please check this!
    3. The situation we have is that there have been systems fielded with ~ 1Meg pull-up and 1Meg pull-down on the CT pin (no capacitor) with Vdd = 3.3V. We need to know how the device will operate in this condition - including over temperature. Will it provide 20msec delay, 300msec delay, sometimes one or the other depending on temperature?

    Please advise!

    Best Regards,

    Steve
  • 0 in reply to Steve Widener
    TI__Genius 12630 points
    Steve,

    I just powered up the TPS3808G01 EVM and the results are as follows:

    With VDD = 3.3V
    CT pin connected to 1Mohm to VDD
    CT pin connected to 1Mohm to GND

    The reset delay is ~317ms (300ms typical).

    I believe this is because the 3.3V is divided evenly between the resistor divider leaving 1.65V at the CT pin which is higher than 1.23V CT pin ref voltage so the device considers this "pulled up to VDD"

    The statement I made before is incorrect because I thought you were using pull-up voltage of 1.65V and a single pull-up resistor. The case you mentioned has pull-up voltage of 3.3V and two equal 1Mohm resistors (a pull up resistor from CT to VDD and a pull down resistor from CT to GND). In this case, we know the voltage at CT pin is 1.65V and this is higher than 1.23V so from the device perspective, the device thinks CT is being pulled up to VDD. This is proven by the delay result of ~300ms.

    -Michael
  • 0 in reply to Michael_DeSando
    TI__Genius 9965 points
    Thanks for the data Michael!

    We need to dig into this one a little deeper due to the criticality of this application.

    Please provide a functional schematic of the CT pin & the logic that determines the delay timing (300msec, 20msec or as a function of the capacitor charging time). With such large resistors, there is a concern that leakage currents into the CT pin could alter operation or perhaps put the device into an unstable state - especially when considering lot variation & wide temperature swings.

    We need to be able to show that there is margin (& how much) over process, Vdd & temperature so that the device will always operate as described (300msec delay mode).

    Steve
  • 0 in reply to Steve Widener
    TI__Genius 12630 points
    Steve,

    I would like more information about the application before determining if this un-recommended implementation should be used. The customer is attempting to use our device outside of what is recommended in the datasheet, and instead of forcing something that is not recommended, I would like to first see why they have it configured this way.

    The TPS3808 datasheet, and what we test for and thus what we guarantee and recommend, uses a single pull-up resistor between 40kohm and 200kohm pulled up to VDD. I am not sure why the customer wants to use 1Mohm resistors. I also don't understand why they are using both a pull-up and pull-down resistor configuration for this Open-Drain output topology. I would like to figure that out before going through the long and expensive process of the testing required in order to "be able to show that there is margin (& how much) over process, Vdd & temperature so that the device will always operate as described (300msec delay mode)".


    And I know the Capacitor Delay logic uses and internal current source and a comparator with a defined reference voltage. The device checks the capacitance on the CT pin initially to determine if an external capacitor is connected, or if the pin is floating (less than 5pF) or if the CT pin is already >1.23V (connected to VDD via pull-up resistor). With the open CT pin (less than 5pF capacitance) or the pin already at or above the reference voltage, the device goes into a fixed timing mode. With the external cap, the capacitor charges up to the reference voltage which creates the delay. This is how it is done in every supervisor. The capacitor delay equation is always derived from the current-voltage relationship defined by every capacitor: I = C dv/dt or in terms of the datasheet equation: Charge current = external capacitance value multiplied by the change in capacitor voltage (0V to the reference voltage) divided by the delay (0 seconds to the time it takes to charge to the ref voltage). We don't have a functional block diagram of the CT pin for the TPS3808. The block diagram just has a high-level block that says "RESET delay logic". If you look at older supervisor devices with programmable delays, you will see the current source and comparator and I don't think there is much more to it.

    If any information or details are sensitive regarding the customer's use case, feel free to email me directly at michaeldesando@ti.com. Thank you!

    -Michael
  • 0 in reply to Michael_DeSando
    TI__Genius 9965 points

    Thanks Michael - taking this off line.