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Original question:

TPS386000: Do MR input and RESET outs have the same ESD tolerance as the analog sense ports?

TPS386000: Do MR input and RESET outs have the same ESD tolerance as the analog sense ports?

Rick Hille
Intellectual 410 points
Part Number: TPS386000

This is now appearing to be a Latch-up issue rather than ESD as initially suspected. The devices appear to fail with roughly the same symptom;  the Vdd to GND pins of the device measures anywhere from 40 to 80-ohms,  and high impedance to any inputs or outputs, or to the substrate pad.  Some or all RESET outputs do not assert with sense input conditions correct for assertion.   

I can now reproduce the failure by invoking soft power shutdown, then momentarily disconnecting and re-connecting the DC input power to the card.  The chip VDD is the first rail that comes up straight from the input DC and normally monitors the various rails on the board.  As it turns out, some of the sense inputs as well as output pullups are fed from rails that have lots of capacitance and do not discharge very quickly.  Cutting the input DC and re-applying it soon after results in the chip briefly being exposed to pins being biased above the immediate Vdd level.  Those bias voltages are well under the Vdd max of 7V and the chip should be able to tolerate this according to the TI answer on Nov 14, 2017 to a post regarding sense inputs being powered when Vdd=0V.  

  • 0
    Guru 140200 points
    Hi Rick,

    when disconnecting lines inductivities come into play which can cause ringing and inductive kick backs. So, during a disconnecting event much higher voltages (positive and negative!) can appear at the pins than might be expected from the static values.

    Filter caps directly from the sense inputs to GND can help a bit.

    Kai
  • 0
    TI__Genius 12630 points
    Rick,

    It sounds like the VDD is somehow shorting to GND via some external or internal path. High impedance at the inputs are OK since the inputs are comparator inputs that should have high impedance. The RESET outputs are connected internally to the Drain of internal FETs so that is also OK to be high impedance when the internal FETs are off.

    I am trying to figure out why the RESET outputs aren't asserting when the sense conditions are met for assertion. And also why is there so much capacitance at the output pins?

    Can you provide a schematic and scope captures showing the power on VDD, SENSE and RESET when the device is not working correctly? Are you using /MR?

    If any information is sensitive, email me directly at michaeldesando@ti.com

    -Michael
  • 0 in reply to Michael_DeSando
    Intellectual 410 points
    Observing the Vdd waveform at power-up revealed an alarming output overshoot of the linear regulator that powers the 386000, reaching brief voltage peaks well over the 7V max rating of Vdd. The overshoot was completely unexpected since the regulator manufacturer's (not TI) design recommendations were followed. The observed scope probe-induced destruction may have just been a misleading interaction with the unpredictable internal state of the die after the overvoltage event, leaving a strong impression that probing somehow caused the failure. The rail clamping diodes that initially seemed to have worked on one board just added to this, furthering the theory that ESD was somehow responsible despite reasonable measures taken to control it on the bench.

    The regulator has been stabilized and no longer overshoots, and the replaced 386000's readily survive power-ups and scope probing, so this issue is solved.