TPS259241 glitch issue on EN signal

Anandraj S

Prodigy 60 points

Hi All,

Please find the block diagram with active component configuration below:

over 6 years ago

0 Rakesh over 6 years ago

TI__Guru* 96001 points

Hi Anandraj,

Looks like your attachment is missing

Regards,
Rakesh

0 Anandraj S over 6 years ago in reply to Rakesh

Prodigy 60 points

Hi Rakesh,

Thanks your reply.Forgot to attached both block diagram and captured waveform.

Please find the block diagram with passive component value below:

Captured waveform below

we are facing glitch issue on EN signals.

why EN glitch is coming on EN signals?if anybody faced similar issue,Please let me know how to solved it.

Thanks & Regards,

Anandraj.S

0 Rakesh over 6 years ago in reply to Anandraj S

TI__Guru* 96001 points

Hi Anandraj,

The glitch is coming from the OTP option/section provided at EN pin. When the input voltage reaches its internal UVLO threshold, all the configuration bits are set properly and that is what causes this glitch. Before the internal UVLO is reached, there is a ~500kΩ of pull up impedance on EN pin, which goes away as soon as the UVLO is crossed. It is harmless to the part’s behavior in the system.

Best Regards,
Rakesh

0 Anandraj S over 6 years ago in reply to Rakesh

Prodigy 60 points

Thanks for your reply.

I got your point . but still I want to avoid glitch on the EN Pin, anyway is there?

one more observation with R2 is open :

when the R2 is open, we are not seen glitch on EN Pin. why ?

Thanks & Regards,

Anandraj.S

0 Rakesh over 6 years ago in reply to Anandraj S

TI__Guru* 96001 points

Hi Anandraj,

It will be seen only when R2 is placed as it forms shunt with internal impedance at EN/UVLO pin.
The glitch can be reduced by scaling down the R1 and R2 by factor 10 or more. In your case check with R1 = 100kohm and R2=14.7kohm

Best Regards,
Rakesh

0 Anandraj S over 6 years ago in reply to Rakesh

Prodigy 60 points

Thanks for your reply.

We have changed the R1 = 100K and R2 = 19K6 in our board, now glitch is reduced.

As per the datasheets, under voltage lock set point formula below:

Vuv=((R1+R2)*VENR)/R2 where VENR-=1.4V

Captured waveform with configuration (R1 = 100k ;R2 = 19K6 ;VENR =1.4V) below:

Theoretical value of under voltage set point (Vuv) = 8.542V.but measured value is 9.72V.

1.Why under voltage set point of theoretical value (8.5V) and measured value(9.72V) are not matching?

2. Recommended Max current on EN pin?

3. Please suggest the values for the configuration below:

Vin = 12V;

under voltage set point Vuv=10V.

current limit thersold limit =3.7A

Setting the output ramp time =2.6ms

R1=?;R2=?;CdVdT=?;RLIM=?.

With Thanks & Regards,

Anandraj.S

0 Rakesh over 6 years ago in reply to Anandraj S

TI__Guru* 96001 points

Hi Anandraj,

The device will be enabled when Vin > Vuvr (8.54V) but the output will start rising only after TON delay.

please use design cal available at www.ti.com/.../toolssoftware and let me know if you have any questions. There are two application examples in the datasheet.

Regards
Rakesh

0 Anandraj S over 6 years ago in reply to Anandraj S

Prodigy 60 points

Thanks for support.

For design parameter we can use that excel.

In that excel they are not mentioned about EN pin max current.

Please let me know max current on EN Pin.

Regards,
Anandraj.S

0 Rakesh over 6 years ago in reply to Anandraj S

TI__Guru* 96001 points

Hi Anandraj,

When R2 not used, R1 should be selected high enough to limit current < 20uA into EN pin

Best Regards,
Rakesh

0 Anandraj S over 6 years ago in reply to Rakesh

Prodigy 60 points

Thanks for your support

Thanks & Regards,

Anandraj.S

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TPS259241 glitch issue on EN signal