Hello everyone,
I'm trying to bring up a custom board similar to the BBB with the AM335x and I can see the steady "CCCCC". Because of a different RAM (Micron MT41K256M16HA-125:E) on my board as on the BBB, I followed these wiki:
_processors.wiki.ti.com/.../Sitara_Linux_Training:_Tuning_the_DDR3_Timings_on_BeagleBoneBlack
in the newest SDK for am335x-evm. When I create an sd-card, I only see this in the terminal:
"U-Boot SPL 2017.01-g590c7d7fe1 (Sep 26 2017 - 18:28:01)" at boot.
/*
* board.c
*
* Board functions for TI AM335X based boards
*
* Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
* GNU General Public License for more details.
*/
#include <common.h>
#include <errno.h>
#include <spl.h>
#include <asm/arch/cpu.h>
#include <asm/arch/hardware.h>
#include <asm/arch/omap.h>
#include <asm/arch/ddr_defs.h>
#include <asm/arch/clock.h>
#include <asm/arch/gpio.h>
#include <asm/arch/mmc_host_def.h>
#include <asm/arch/sys_proto.h>
#include <asm/io.h>
#include <asm/emif.h>
#include <asm/gpio.h>
#include <i2c.h>
#include <miiphy.h>
#include <cpsw.h>
#include "board.h"
#include "pmic.h"
#include "tps65217.h"
DECLARE_GLOBAL_DATA_PTR;
static struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE;
#if defined(CONFIG_SPL_BUILD)
static struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE;
#endif
/* MII mode defines */
#define MII_MODE_ENABLE 0x0
static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
static struct am335x_baseboard_id __attribute__((section (".data"))) header;
/* UART Defines */
#if defined(CONFIG_SPL_BUILD)
/**
* tps65217_reg_read() - Generic function that can read a TPS65217 register
* @src_reg: Source register address
* @src_val: Address of destination variable
*/
unsigned char tps65217_reg_read(uchar src_reg, uchar *src_val)
{
if (i2c_read(TPS65217_CHIP_PM, src_reg, 1, src_val, 1))
return 1;
return 0;
}
/**
* tps65217_reg_write() - Generic function that can write a TPS65217 PMIC
* register or bit field regardless of protection
* level.
*
* @prot_level: Register password protection.
* use PROT_LEVEL_NONE, PROT_LEVEL_1, or PROT_LEVEL_2
* @dest_reg: Register address to write.
* @dest_val: Value to write.
* @mask: Bit mask (8 bits) to be applied. Function will only
* change bits that are set in the bit mask.
*
* @return: 0 for success, 1 for failure.
*/
int tps65217_reg_write(uchar prot_level, uchar dest_reg,
uchar dest_val, uchar mask)
{
uchar read_val;
uchar xor_reg;
/* if we are affecting only a bit field, read dest_reg and apply the mask */
if (mask != MASK_ALL_BITS) {
if (i2c_read(TPS65217_CHIP_PM, dest_reg, 1, &read_val, 1))
return 1;
read_val &= (~mask);
read_val |= (dest_val & mask);
dest_val = read_val;
}
if (prot_level > 0) {
xor_reg = dest_reg ^ PASSWORD_UNLOCK;
if (i2c_write(TPS65217_CHIP_PM, PASSWORD, 1, &xor_reg, 1))
return 1;
}
if (i2c_write(TPS65217_CHIP_PM, dest_reg, 1, &dest_val, 1))
return 1;
if (prot_level == PROT_LEVEL_2) {
if (i2c_write(TPS65217_CHIP_PM, PASSWORD, 1, &xor_reg, 1))
return 1;
if (i2c_write(TPS65217_CHIP_PM, dest_reg, 1, &dest_val, 1))
return 1;
}
return 0;
}
int tps65217_voltage_update(unsigned char dc_cntrl_reg, unsigned char volt_sel)
{
if ((dc_cntrl_reg != DEFDCDC1) && (dc_cntrl_reg != DEFDCDC2)
&& (dc_cntrl_reg != DEFDCDC3))
return 1;
/* set voltage level */
if (tps65217_reg_write(PROT_LEVEL_2, dc_cntrl_reg, volt_sel, MASK_ALL_BITS))
return 1;
/* set GO bit to initiate voltage transition */
if (tps65217_reg_write(PROT_LEVEL_2, DEFSLEW, DCDC_GO, DCDC_GO))
return 1;
return 0;
}
#define UART_RESET (0x1 << 1)
#define UART_CLK_RUNNING_MASK 0x1
#define UART_SMART_IDLE_EN (0x1 << 0x3)
static void rtc32k_enable(void)
{
struct rtc_regs *rtc = (struct rtc_regs *)AM335X_RTC_BASE;
/*
* Unlock the RTC's registers. For more details please see the
* RTC_SS section of the TRM. In order to unlock we need to
* write these specific values (keys) in this order.
*/
writel(0x83e70b13, &rtc->kick0r);
writel(0x95a4f1e0, &rtc->kick1r);
/* Enable the RTC 32K OSC by setting bits 3 and 6. */
writel((1 << 3) | (1 << 6), &rtc->osc);
}
static const struct ddr_data ddr2_data = {
.datardsratio0 = ((MT47H128M16RT25E_RD_DQS<<30) |
(MT47H128M16RT25E_RD_DQS<<20) |
(MT47H128M16RT25E_RD_DQS<<10) |
(MT47H128M16RT25E_RD_DQS<<0)),
.datawdsratio0 = ((MT47H128M16RT25E_WR_DQS<<30) |
(MT47H128M16RT25E_WR_DQS<<20) |
(MT47H128M16RT25E_WR_DQS<<10) |
(MT47H128M16RT25E_WR_DQS<<0)),
.datawiratio0 = ((MT47H128M16RT25E_PHY_WRLVL<<30) |
(MT47H128M16RT25E_PHY_WRLVL<<20) |
(MT47H128M16RT25E_PHY_WRLVL<<10) |
(MT47H128M16RT25E_PHY_WRLVL<<0)),
.datagiratio0 = ((MT47H128M16RT25E_PHY_GATELVL<<30) |
(MT47H128M16RT25E_PHY_GATELVL<<20) |
(MT47H128M16RT25E_PHY_GATELVL<<10) |
(MT47H128M16RT25E_PHY_GATELVL<<0)),
.datafwsratio0 = ((MT47H128M16RT25E_PHY_FIFO_WE<<30) |
(MT47H128M16RT25E_PHY_FIFO_WE<<20) |
(MT47H128M16RT25E_PHY_FIFO_WE<<10) |
(MT47H128M16RT25E_PHY_FIFO_WE<<0)),
.datawrsratio0 = ((MT47H128M16RT25E_PHY_WR_DATA<<30) |
(MT47H128M16RT25E_PHY_WR_DATA<<20) |
(MT47H128M16RT25E_PHY_WR_DATA<<10) |
(MT47H128M16RT25E_PHY_WR_DATA<<0)),
.datauserank0delay = MT47H128M16RT25E_PHY_RANK0_DELAY,
.datadldiff0 = PHY_DLL_LOCK_DIFF,
};
static const struct cmd_control ddr2_cmd_ctrl_data = {
.cmd0csratio = MT47H128M16RT25E_RATIO,
.cmd0dldiff = MT47H128M16RT25E_DLL_LOCK_DIFF,
.cmd0iclkout = MT47H128M16RT25E_INVERT_CLKOUT,
.cmd1csratio = MT47H128M16RT25E_RATIO,
.cmd1dldiff = MT47H128M16RT25E_DLL_LOCK_DIFF,
.cmd1iclkout = MT47H128M16RT25E_INVERT_CLKOUT,
.cmd2csratio = MT47H128M16RT25E_RATIO,
.cmd2dldiff = MT47H128M16RT25E_DLL_LOCK_DIFF,
.cmd2iclkout = MT47H128M16RT25E_INVERT_CLKOUT,
};
static const struct emif_regs ddr2_emif_reg_data = {
.sdram_config = MT47H128M16RT25E_EMIF_SDCFG,
.ref_ctrl = MT47H128M16RT25E_EMIF_SDREF,
.sdram_tim1 = MT47H128M16RT25E_EMIF_TIM1,
.sdram_tim2 = MT47H128M16RT25E_EMIF_TIM2,
.sdram_tim3 = MT47H128M16RT25E_EMIF_TIM3,
.emif_ddr_phy_ctlr_1 = MT47H128M16RT25E_EMIF_READ_LATENCY,
};
static const struct ddr_data ddr3_data = {
.datardsratio0 = MT41J128MJT125_RD_DQS,
.datawdsratio0 = MT41J128MJT125_WR_DQS,
.datafwsratio0 = MT41J128MJT125_PHY_FIFO_WE,
.datawrsratio0 = MT41J128MJT125_PHY_WR_DATA,
.datadldiff0 = PHY_DLL_LOCK_DIFF,
};
static const struct ddr_data ddr3_beagleblack_data = {
.datardsratio0 = MT41K256M16HA125E_RD_DQS,
.datawdsratio0 = MT41K256M16HA125E_WR_DQS,
.datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
.datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
.datadldiff0 = PHY_DLL_LOCK_DIFF,
};
static const struct ddr_data ddr3_evm_data = {
.datardsratio0 = MT41J512M8RH125_RD_DQS,
.datawdsratio0 = MT41J512M8RH125_WR_DQS,
.datafwsratio0 = MT41J512M8RH125_PHY_FIFO_WE,
.datawrsratio0 = MT41J512M8RH125_PHY_WR_DATA,
.datadldiff0 = PHY_DLL_LOCK_DIFF,
};
static const struct cmd_control ddr3_cmd_ctrl_data = {
.cmd0csratio = MT41J128MJT125_RATIO,
.cmd0dldiff = MT41J128MJT125_DLL_LOCK_DIFF,
.cmd0iclkout = MT41J128MJT125_INVERT_CLKOUT,
.cmd1csratio = MT41J128MJT125_RATIO,
.cmd1dldiff = MT41J128MJT125_DLL_LOCK_DIFF,
.cmd1iclkout = MT41J128MJT125_INVERT_CLKOUT,
.cmd2csratio = MT41J128MJT125_RATIO,
.cmd2dldiff = MT41J128MJT125_DLL_LOCK_DIFF,
.cmd2iclkout = MT41J128MJT125_INVERT_CLKOUT,
};
static const struct cmd_control ddr3_beagleblack_cmd_ctrl_data = {
.cmd0csratio = MT41K256M16HA125E_RATIO,
.cmd0dldiff = MT41K256M16HA125E_DLL_LOCK_DIFF,
.cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
.cmd1csratio = MT41K256M16HA125E_RATIO,
.cmd1dldiff = MT41K256M16HA125E_DLL_LOCK_DIFF,
.cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
.cmd2csratio = MT41K256M16HA125E_RATIO,
.cmd2dldiff = MT41K256M16HA125E_DLL_LOCK_DIFF,
.cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
};
static const struct cmd_control ddr3_evm_cmd_ctrl_data = {
.cmd0csratio = MT41J512M8RH125_RATIO,
.cmd0dldiff = MT41J512M8RH125_DLL_LOCK_DIFF,
.cmd0iclkout = MT41J512M8RH125_INVERT_CLKOUT,
.cmd1csratio = MT41J512M8RH125_RATIO,
.cmd1dldiff = MT41J512M8RH125_DLL_LOCK_DIFF,
.cmd1iclkout = MT41J512M8RH125_INVERT_CLKOUT,
.cmd2csratio = MT41J512M8RH125_RATIO,
.cmd2dldiff = MT41J512M8RH125_DLL_LOCK_DIFF,
.cmd2iclkout = MT41J512M8RH125_INVERT_CLKOUT,
};
static struct emif_regs ddr3_emif_reg_data = {
.sdram_config = MT41J128MJT125_EMIF_SDCFG,
.ref_ctrl = MT41J128MJT125_EMIF_SDREF,
.sdram_tim1 = MT41J128MJT125_EMIF_TIM1,
.sdram_tim2 = MT41J128MJT125_EMIF_TIM2,
.sdram_tim3 = MT41J128MJT125_EMIF_TIM3,
.zq_config = MT41J128MJT125_ZQ_CFG,
.emif_ddr_phy_ctlr_1 = MT41J128MJT125_EMIF_READ_LATENCY |
PHY_EN_DYN_PWRDN,
};
static struct emif_regs ddr3_beagleblack_emif_reg_data = {
.sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
.ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
.sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
.sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
.sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
.zq_config = MT41K256M16HA125E_ZQ_CFG,
.emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY,
};
static struct emif_regs ddr3_evm_emif_reg_data = {
.sdram_config = MT41J512M8RH125_EMIF_SDCFG,
.ref_ctrl = MT41J512M8RH125_EMIF_SDREF,
.sdram_tim1 = MT41J512M8RH125_EMIF_TIM1,
.sdram_tim2 = MT41J512M8RH125_EMIF_TIM2,
.sdram_tim3 = MT41J512M8RH125_EMIF_TIM3,
.zq_config = MT41J512M8RH125_ZQ_CFG,
.emif_ddr_phy_ctlr_1 = MT41J512M8RH125_EMIF_READ_LATENCY |
PHY_EN_DYN_PWRDN,
};
static const struct ddr_data ddr3_bbb_data = {
.datardsratio0 = MT41K256M16HA125ET_RD_DQS,
.datawdsratio0 = MT41K256M16HA125ET_WR_DQS,
.datafwsratio0 = MT41K256M16HA125ET_PHY_FIFO_WE,
.datawrsratio0 = MT41K256M16HA125ET_PHY_WR_DATA,
.datadldiff0 = PHY_DLL_LOCK_DIFF,
};
static const struct cmd_control ddr3_bbb_cmd_ctrl_data = {
.cmd0csratio = MT41K256M16HA125ET_RATIO,
.cmd0dldiff = MT41K256M16HA125ET_DLL_LOCK_DIFF,
.cmd0iclkout = MT41K256M16HA125ET_INVERT_CLKOUT,
.cmd1csratio = MT41K256M16HA125ET_RATIO,
.cmd1dldiff = MT41K256M16HA125ET_DLL_LOCK_DIFF,
.cmd1iclkout = MT41K256M16HA125ET_INVERT_CLKOUT,
.cmd2csratio = MT41K256M16HA125ET_RATIO,
.cmd2dldiff = MT41K256M16HA125ET_DLL_LOCK_DIFF,
.cmd2iclkout = MT41K256M16HA125ET_INVERT_CLKOUT,
};
static struct emif_regs ddr3_bbb_emif_reg_data = {
.sdram_config = MT41K256M16HA125ET_EMIF_SDCFG,
.ref_ctrl = MT41K256M16HA125ET_EMIF_SDREF,
.sdram_tim1 = MT41K256M16HA125ET_EMIF_TIM1,
.sdram_tim2 = MT41K256M16HA125ET_EMIF_TIM2,
.sdram_tim3 = MT41K256M16HA125ET_EMIF_TIM3,
.zq_config = MT41K256M16HA125ET_ZQ_CFG,
.emif_ddr_phy_ctlr_1 = MT41K256M16HA125ET_EMIF_READ_LATENCY | PHY_EN_DYN_PWRDN,
};
void am33xx_spl_board_init(void)
{
int mpu_vdd, mpu_pll, sil_rev;
uchar pmic_status_reg;
int usb_cur_lim;
/* Assume PG 1.0 */
mpu_pll = MPUPLL_M_720;
sil_rev = readl(&cdev->deviceid) >> 28;
if (sil_rev == 1)
/* PG 2.0, efuse may not be set. */
mpu_pll = MPUPLL_M_800;
else if (sil_rev >= 2) {
/* Check what the efuse says our max speed is. */
int efuse_arm_mpu_max_freq;
efuse_arm_mpu_max_freq = readl(&cdev->efuse_sma);
if ((efuse_arm_mpu_max_freq & DEVICE_ID_MASK) ==
AM335X_ZCZ_1000)
mpu_pll = MPUPLL_M_1000;
else if ((efuse_arm_mpu_max_freq & DEVICE_ID_MASK) ==
AM335X_ZCZ_800)
mpu_pll = MPUPLL_M_800;
}
if (i2c_probe(TPS65217_CHIP_PM))
return;
if (tps65217_reg_read(STATUS, &pmic_status_reg))
return;
/*
* Increase USB current limit to 1300mA or 1800mA and set
* the MPU voltage controller as needed.
*/
if (mpu_pll == MPUPLL_M_1000) {
usb_cur_lim = USB_INPUT_CUR_LIMIT_1800MA;
mpu_vdd = DCDC_VOLT_SEL_1325MV;
} else {
usb_cur_lim = USB_INPUT_CUR_LIMIT_1300MA;
mpu_vdd = DCDC_VOLT_SEL_1275MV;
}
if (tps65217_reg_write(PROT_LEVEL_NONE, POWER_PATH,
usb_cur_lim, USB_INPUT_CUR_LIMIT_MASK))
printf("tps65217_reg_write failure\n");
/* Set DCDC3 (CORE) voltage to 1.125V */
if (tps65217_voltage_update(DEFDCDC3, DCDC_VOLT_SEL_1125MV)) {
printf("tps65217_voltage_update failure\n");
return;
}
/* Set CORE Frequency to what we detected */
core_pll_config(OPP_100);
/* Set DCDC2 (MPU) voltage to 1.275V */
if (tps65217_voltage_update(DEFDCDC2, mpu_vdd)) {
printf("tps65217_voltage_update failure\n");
return;
}
/* Set MPU Frequency to what we detected */
mpu_pll_config(mpu_pll);
/*
* Set LDO3, LDO4 output voltage to 3.3V for Beaglebone.
*/
if (tps65217_reg_write(PROT_LEVEL_2, DEFLS1,
LDO_VOLTAGE_OUT_3_3, LDO_MASK))
printf("tps65217_reg_write failure\n");
if (tps65217_reg_write(PROT_LEVEL_2, DEFLS2,
LDO_VOLTAGE_OUT_3_3, LDO_MASK))
printf("tps65217_reg_write failure\n");
if (!(pmic_status_reg & PWR_SRC_AC_BITMASK)) {
printf("No AC power, disabling frequency switch\n");
return;
}
}
#endif
/*
* early system init of muxing and clocks.
*/
void s_init(void)
{
volatile int myVar = 1;
__maybe_unused struct am335x_baseboard_id header;
/* WDT1 is already running when the bootloader gets control
* Disable it to avoid "random" resets
*/
writel(0xAAAA, &wdtimer->wdtwspr);
while (readl(&wdtimer->wdtwwps) != 0x0)
;
writel(0x5555, &wdtimer->wdtwspr);
while (readl(&wdtimer->wdtwwps) != 0x0)
;
#if defined(CONFIG_SPL_BUILD)
/* Setup the PLLs and the clocks for the peripherals */
pll_init();
/* Enable RTC32K clock */
rtc32k_enable();
/* UART softreset */
u32 regVal;
#ifdef CONFIG_SERIAL1
enable_uart0_pin_mux();
#endif /* CONFIG_SERIAL1 */
#ifdef CONFIG_SERIAL2
enable_uart1_pin_mux();
#endif /* CONFIG_SERIAL2 */
#ifdef CONFIG_SERIAL3
enable_uart2_pin_mux();
#endif /* CONFIG_SERIAL3 */
#ifdef CONFIG_SERIAL4
enable_uart3_pin_mux();
#endif /* CONFIG_SERIAL4 */
#ifdef CONFIG_SERIAL5
enable_uart4_pin_mux();
#endif /* CONFIG_SERIAL5 */
#ifdef CONFIG_SERIAL6
enable_uart5_pin_mux();
#endif /* CONFIG_SERIAL6 */
regVal = readl(&uart_base->uartsyscfg);
regVal |= UART_RESET;
writel(regVal, &uart_base->uartsyscfg);
while ((readl(&uart_base->uartsyssts) &
UART_CLK_RUNNING_MASK) != UART_CLK_RUNNING_MASK)
;
/* Disable smart idle */
regVal = readl(&uart_base->uartsyscfg);
regVal |= UART_SMART_IDLE_EN;
writel(regVal, &uart_base->uartsyscfg);
gd = &gdata;
preloader_console_init();
enable_i2c0_pin_mux();
i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
config_ddr(400, MT41K256M16HA125ET_IOCTRL_VALUE, &ddr3_bbb_data,
&ddr3_bbb_cmd_ctrl_data, &ddr3_bbb_emif_reg_data);
while(myVar);
#endif
}
/*
* Basic board specific setup. Pinmux has been handled already.
*/
int board_init(void)
{
i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
gd->bd->bi_boot_params = PHYS_DRAM_1 + 0x100;
gpmc_init();
return 0;
}
#ifdef CONFIG_BOARD_LATE_INIT
int board_late_init(void)
{
#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
/* Now set variables based on board. */
setenv("board_name", "A335BONE\0");
#endif
return 0;
}
#endif
#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
(defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
static void cpsw_control(int enabled)
{
/* VTP can be added here */
return;
}
static struct cpsw_slave_data cpsw_slaves[] = {
{
.slave_reg_ofs = 0x208,
.sliver_reg_ofs = 0xd80,
.phy_id = 0,
},
{
.slave_reg_ofs = 0x308,
.sliver_reg_ofs = 0xdc0,
.phy_id = 1,
},
};
static struct cpsw_platform_data cpsw_data = {
.mdio_base = AM335X_CPSW_MDIO_BASE,
.cpsw_base = AM335X_CPSW_BASE,
.mdio_div = 0xff,
.channels = 8,
.cpdma_reg_ofs = 0x800,
.slaves = 1,
.slave_data = cpsw_slaves,
.ale_reg_ofs = 0xd00,
.ale_entries = 1024,
.host_port_reg_ofs = 0x108,
.hw_stats_reg_ofs = 0x900,
.mac_control = (1 << 5),
.control = cpsw_control,
.host_port_num = 0,
.version = CPSW_CTRL_VERSION_2,
};
#endif
#if defined(CONFIG_DRIVER_TI_CPSW) || \
(defined(CONFIG_USB_ETHER) && defined(CONFIG_MUSB_GADGET))
int board_eth_init(bd_t *bis)
{
int rv, n = 0;
uint8_t mac_addr[6];
uint32_t mac_hi, mac_lo;
/* try reading mac address from efuse */
mac_lo = readl(&cdev->macid0l);
mac_hi = readl(&cdev->macid0h);
mac_addr[0] = mac_hi & 0xFF;
mac_addr[1] = (mac_hi & 0xFF00) >> 8;
mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
mac_addr[4] = mac_lo & 0xFF;
mac_addr[5] = (mac_lo & 0xFF00) >> 8;
#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
(defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
if (!getenv("ethaddr")) {
printf("<ethaddr> not set. Validating first E-fuse MAC\n");
if (is_valid_ether_addr(mac_addr))
eth_setenv_enetaddr("ethaddr", mac_addr);
}
writel(MII_MODE_ENABLE, &cdev->miisel);
cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if =
PHY_INTERFACE_MODE_MII;
rv = cpsw_register(&cpsw_data);
if (rv < 0)
printf("Error %d registering CPSW switch\n", rv);
else
n += rv;
#endif
#if defined(CONFIG_USB_ETHER) && \
(!defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_USBETH_SUPPORT))
if (is_valid_ether_addr(mac_addr))
eth_setenv_enetaddr("usbnet_devaddr", mac_addr);
rv = usb_eth_initialize(bis);
if (rv < 0)
printf("Error %d registering USB_ETHER\n", rv);
else
n += rv;
#endif
return n;
}
#endif
After building my own u-boot (command:"make u-boot") and replacing the MLO and u-boot.img, nothing appears at boot on the terminal.
I also tried to enable debug (#define DEBUG in am335x_evm.h), but nothing is vissible.
I read in another thread, that the wiki is a kind of obsolet for the current SDK. If that is correct, is somewhere a current version? Do I only have to replace the MLO and the u-boot.img? Where I have to define the DEBUG?
Thanks very much for your help.
Kind regards
Eric
