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AM5728: mcaspCreateChan cause data storage issue on ARM side

Shine
Genius 13655 points
Part Number: AM5728
Other Parts Discussed in Thread: AM5708

Hello Champs,

Customer used SDK ti-processor-sdk-rtos-am57xx-evm-05.00.00.15-Linux-x86-Install.bin. He found the mcaspCreateChan cause file storage issue on ARM side. The data is changed, thus the CRC failed. 

The left is the wrong data and the right is the correct data.


He tracked the code and found that when using mcaspCreateChan to create both RX and TX channels, the problem will occur. If only creating RX or TX channel, the problem will not occur.


Below is the test steps.

Only initializing IO stream
Buffer stream BUF is not initialized.
In Create_Stream, mcaspCreateChan created Mcasp channel 4 both TX and RX .
Creating a 1G file aaa, then running below commands on the board.

cp aaa bbb
sync
diff aaa bbb
aaa is different from bbb. 
If only creating Mcasp channel 4 Tx or RX, aaa is the same to bbb.

Thanks.
Best Regards

Shine

  • 0
    Prodigy 150 points

    Dear Shine,

    First of all, thank you for forwarding the question.

    This problem occurs with AM5708.

    In effect, Memory data is changed.

    Best Regards

    June

  • 0 in reply to user6342709
    TI__Guru 50045 points

    Could you make sure the RX and TX buffers are not overlapping each other?

  • 0 in reply to Stanley Liu
    Prodigy 150 points

    I'm sure they don't overlap.

    Part of the code is as follows.

  • 0 in reply to user6342709
    Prodigy 150 points

    Check MD5 like this,

    md5sum is changed.

  • 0
    Prodigy 150 points

    There is no progress on this issue at present,so i tried the following.

    1.If i do not use McAspCreateChan to create the TX channel, and find that the RX channel callback cannot enter, resulting in the inability to obtain the recording data. Why is that?

    2.If i use McAspCreateChan to create the TX channel, only create and do nothing else. The phenomenon still exists.

    I am not clear about whether the DSP and ARM programs need to do memory mapping and partition the physical address of memory.

  • 0 in reply to user6342709
    Prodigy 150 points

    I used memtester to test memory data, and executed command "./memtester 500 1" on the arm side.

    I have confirmed it several times, and the results are as follows.

    1. If I bind two McAsp devices, create TX channel and RX channel, and then read and write to buffer, the memory data will be changed.

    2. If I bind two Mcasp devices, create TX channel and RX channel, but don't read and write to buffer, the memory data will not be changed.

    3. If I bind two Mcasp devices, create TX channel, but don't create RX channel, then read and write buffer, the memory data will not be changed.

    4. If I bind one McAsp device, the result will be the same as 1, 2, and 3.

    5. If I don't run the DSP program, the memory data won't be changed.

  • 0
    TI__Mastermind 23125 points

    Shine, June, 

    I have a few questions regarding to the tests you've done so far:

    1. Can you confirm what is the memory partition between DSP and ARM in your system?

    2. In later post it seems you first create TX chan on McASP4 and McASP5, then create RX channel on them again. Can you confirm which serializer pins of each McASP that you used for TX / RX?

    3. Commands you issued:

        >>cp aaa bbb

        >>sync 

        >> diff aaa bbb

    were these executed from ARM side, under Linux?

    Thanks

    Jian

  • 0 in reply to jian35385
    TI__Mastermind 23125 points

    also please confirm if the McASP test code was running on the DSP or the ARM. 

    thanks

    jian

  • 0 in reply to jian35385
    TI__Mastermind 23125 points

    sorry for the multiple post - please also clarify where the is the filesystem located. 

    Jian

  • 0 in reply to jian35385
    Prodigy 150 points

    Jian,

    1. CMA

    config.bld

    rsc_table_vayu_dsp.c

    The addresses seen in the config.bld file are virtual addresses, and in the rsc_table_vayu_dsp.c file are physical address. Is that?

  • 0 in reply to jian35385
    Prodigy 150 points

    2. 

    3. Yes. It's more accurate to use command memtester.

    Thanks

    June

  • 0 in reply to user6342709
    TI__Mastermind 23125 points

    Jun, 

    Tony sent your map file via email and he noticed that DSP's "EXT_CODE", "EXT_DATA", "EXT_HEAP" sections started at 0x95000000 in DDR, while Linux only reserved starting from 0x9580000.

    Tony mentioned you are going to modify config.bld file. Were you able to fix the memory partition and retry tests?

    regards

    Jian

  • 0 in reply to jian35385
    Prodigy 150 points

    Jian,

    I modified the config.bld file, and test again. But the DSP program cannot execute.

    modified the config.bld file,

    /*  Memory Map for ti.platforms.evmDRA7XX:dsp1 and ti.platforms.evmDRA7XX:dsp2
 *
 *  --- External Memory ---
 *  Virtual     Physical        Size            Comment
 *  ------------------------------------------------------------------------
 *  9500_4000   ????_????    10_0000  (  ~1 MB) EXT_CODE
 *  9510_0000   ????_????    10_0000  (   1 MB) EXT_DATA
 *  9520_0000   ????_????    30_0000  (   3 MB) EXT_HEAP
 *  9F00_0000   9F00_0000     6_0000  ( 384 kB) TRACE_BUF
 *  9F06_0000   9F06_0000     1_0000  (  64 kB) EXC_DATA
 *  9F07_0000   9F07_0000     2_0000  ( 128 kB) PM_DATA (Power mgmt)
 */
var evmDRA7XX_ExtMemMapDsp = {
    EXT_CODE: {
        name: "EXT_CODE",
        base: 0x95800000,
        len:  0x00100000,
        space: "code",
        access: "RWX"
    },
    EXT_DATA: {
        name: "EXT_DATA",
        base: 0x95900000,
        len:  0x00500000,
        space: "data",
        access: "RW"
    },
    EXT_HEAP: {
        name: "EXT_HEAP",
        base: 0x95e00000,
        len:  0x00300000,
        space: "data",
        access: "RW"
    },
    TRACE_BUF: {
        name: "TRACE_BUF",
        base: 0x9F000000,
        len:  0x00060000,
        space: "data",
        access: "RW"
    },
    EXC_DATA: {
        name: "EXC_DATA",
        base: 0x9F060000,
        len:  0x00010000,
        space: "data",
        access: "RW"
    },
    PM_DATA: {
        name: "PM_DATA",
        base: 0x9F070000,
        len:  0x00020000,
        space: "data",
        access: "RWX"  /* should this have execute perm? */
    },
};

    modified the rsc_table_vayu_dsp.c file,

    #define DSP_MEM_TEXT 0x95800000
/* Co-locate alongside TILER region for easier flushing */
#define DSP_MEM_IOBUFS 0x80000000
#define DSP_MEM_DATA 0x95900000
#define DSP_MEM_HEAP 0x95e00000

    regards

    June

  • 0 in reply to jian35385
    TI__Mastermind 29622 points

    Jian,

    in rsc_table_vayu_dsp.h, defined DSP memory resource, address and size same as in config.bld. how to modify it to avoid overlap with Linux? change both rsc_ta ble_vayu_dsp.h and config.h? or change only one of it? which one?

     rsc_table_vayu_dsp.h:
    #define DSP_MEM_TEXT 0x95000000
    /* Co-locate alongside TILER region for easier flushing */
    #define DSP_MEM_IOBUFS 0x80000000
    #define DSP_MEM_DATA 0x95100000
    #define DSP_MEM_HEAP 0x95200000

    #define DSP_MEM_IPC_DATA 0x9F000000
    #define DSP_MEM_IPC_VRING 0xA0000000
    #define DSP_MEM_RPMSG_VRING0 0xA0000000
    #define DSP_MEM_RPMSG_VRING1 0xA0004000
    #define DSP_MEM_VRING_BUFS0 0xA0040000
    #define DSP_MEM_VRING_BUFS1 0xA0080000

    #define DSP_MEM_IPC_VRING_SIZE SZ_1M
    #define DSP_MEM_IPC_DATA_SIZE SZ_1M
    #define DSP_MEM_TEXT_SIZE SZ_1M
    #define DSP_MEM_DATA_SIZE SZ_1M
    #define DSP_MEM_HEAP_SIZE (SZ_1M * 3)
    #define DSP_MEM_IOBUFS_SIZE (SZ_1M * 90)

     

    config.bld

    /* Memory Map for DSP1
    *
    * --- External Memory ---
    * Virtual Physical Size Comment
    * ------------------------------------------------------------------------
    * 9500_0000 ???0_0000 10_0000 ( ~1 MB) EXT_CODE
    * 9510_0000 ???0_0000 10_0000 ( 1 MB) EXT_DATA
    * 9520_0000 ???0_0000 30_0000 ( 3 MB) EXT_HEAP
    * 9F00_0000 ???0_0000 6_0000 ( 384 kB) TRACE_BUF
    * 9F06_0000 ???6_0000 1_0000 ( 64 kB) EXC_DATA
    * 9F07_0000 ???7_0000 2_0000 ( 128 kB) PM_DATA (Power mgmt)
    */
    var evmDRA7XX_ExtMemMapDsp = {
    EXT_CODE: {
    name: "EXT_CODE",
    base: 0x95000000,
    len: 0x00100000,
    space: "code",
    access: "RWX"
    },
    EXT_DATA: {
    name: "EXT_DATA",
    base: 0x95100000,
    len: 0x00100000,
    space: "data",
    access: "RW"
    },
    EXT_HEAP: {
    name: "EXT_HEAP",
    base: 0x95200000,
    len: 0x00300000,
    space: "data",
    access: "RW"
    },
    TRACE_BUF: {
    name: "TRACE_BUF",
    base: 0x9F000000,
    len: 0x00060000,
    space: "data",
    access: "RW"
    },
    EXC_DATA: {
    name: "EXC_DATA",
    base: 0x9F060000,
    len: 0x00010000,
    space: "data",
    access: "RW"
    },
    PM_DATA: {
    name: "PM_DATA",
    base: 0x9F070000,
    len: 0x00020000,
    space: "data",
    access: "RWX" /* should this have execute perm? */
    },
    SR_0: {
    name: evmDRA7XX_SR_0.name,
    base: evmDRA7XX_SR_0.base,
    len: evmDRA7XX_SR_0.len,
    space: "data",
    access: "RW"
    }
    };

     

  • 0 in reply to jian35385
    Prodigy 150 points

    The McASP test code was running on the DSP.

    You said, "please also clarify where the is the filesystem located".

    Sorry, I don't have any idea what that means.

    am570x-mid.dts

    Fullscreen 2806.am570x-mid.dts.txt Download 
    /*
 * Copyright (C) 2015-2016 Texas Instruments Incorporated - http://www.ti.com/
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */
/dts-v1/;

#include "dra72x.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/clk/ti-dra7-atl.h>
#include "am57xx-idk-common.dtsi"

/ {
	model = "TI AM5718 IDK";
	compatible = "ti,am5718-idk", "ti,am5718", "ti,dra7";

	chosen {
		 bootargs = "console=ttyO2,115200n8 root=/dev/mmcblk0p2 rw rootfstype=ext4 rootwait lpj=61475";
		 //bootargs = "console=ttyO2,115200n8 root=/dev/mmcblk1p2 rw rootfstype=ext4 rootwait";
	};
	aliases {
		ethernet4 = &pruss1_emac0;
		ethernet5 = &pruss1_emac1;
        /delete-property/ rtc1;
        rtc0 = &rv3028; 
                //sound0 = &sound0;
                sound1 = &hdmi;
		/delete-property/ ethernet2;
		/delete-property/ ethernet3;
		/delete-property/ ethernet4;
		/delete-property/ ethernet5;
		display0 = &lcd;
		display1 = &hdmi0;
	};

    /delete-node/ pruss1_eth;
    /delete-node/ pruss2_eth;
    /delete-node/ leds-iio;
    /delete-node/ encoder@0;

    lcd_bl: backlight {
        compatible = "pwm-backlight";
        pwms = <&ehrpwm1 0 50000 0>;
        //pwms = <&ecap0 0 50000 1>;
        brightness-levels = <1 25 50 75 128 158 175 200 220 254>;
        default-brightness-level = <4>;
        //enable-gpios = <&gpio5 6 GPIO_ACTIVE_HIGH>;
    };

    lcd: display {
         compatible = "panel-dpi";

         label = "lcd";

         enable-gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>;

         backlight = <&lcd_bl>;

         /*panel-timing {
             clock-frequency = <51000000>;
             hactive = <1024>;
             vactive = <600>;
             hfront-porch = <290>;
             hback-porch = <20>;
             hsync-len = <10>;
             vback-porch = <20>;
             vfront-porch = <10>;
             vsync-len = <5>;
             hsync-active = <0>;
             vsync-active = <0>;
             de-active = <1>;
             pixelclk-active = <0>;
         };*/
	panel-timing {
		clock-frequency = <65000000>;
		hactive = <1280>;
		vactive = <800>;
		hfront-porch = <24>;
		hback-porch = <24>;
		hsync-len = <2>;
		vfront-porch = <5>;
		vback-porch = <5>;
		vsync-len = <2>;
		hsync-active = <0>;
		vsync-active = <0>;
		de-active = <1>;
		pixelclk-active = <0>;
	};

         port {
            lcd_in: endpoint {
            remote-endpoint = <&dpi_out>;
            };
         };
     };

	memory@80000000 {
		device_type = "memory";
		reg = <0x0 0x80000000 0x0 0x40000000>;
	};

    ocp{
        /delete-node/ sata@4a141100;
        /delete-node/ rtc@48838000;
        /delete-node/ omap_dwc3_3@48900000;
    };

	evm_12v0: fixedregulator-evm12v0 {
		/* main supply */
		compatible = "regulator-fixed";
		regulator-name = "evm_12v0";
		regulator-min-microvolt = <12000000>;
		regulator-max-microvolt = <12000000>;
		regulator-always-on;
		regulator-boot-on;
		/*gpio = <&gpio6 13 0>;
		enable-active-high;*/
	};

	evm_5v0: fixedregulator-evm5v0 {
		/* Output 1 of TPS43351QDAPRQ1 on dra72-evm */
		/* Output 1 of LM5140QRWGTQ1 on dra71-evm */
		compatible = "regulator-fixed";
		regulator-name = "evm_5v0";
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
		vin-supply = <&evm_12v0>;
		regulator-always-on;
		regulator-boot-on;
	};

	vsys_3v3: fixedregulator-vsys3v3 {
		/* Output 2 of TPS43351QDAPRQ1 on dra72-evm */
		/* Output 2 of LM5140QRWGTQ1 on dra71-evm */
		compatible = "regulator-fixed";
		regulator-name = "vsys_3v3";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		vin-supply = <&evm_12v0>;
		regulator-always-on;
		regulator-boot-on;
	};

	emmcex_3v3: fixedregulator-emmcex3v3 {
		compatible = "regulator-fixed";
		regulator-name = "emmcex_3v3";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		vin-supply = <&evm_12v0>;
		gpio = <&gpio4 5 0>;
		startup-delay-us = <2000>;
		enable-active-high;
	};

	emmcex_oe: fixedregulator-emmcexoe {
		compatible = "regulator-fixed";
		regulator-name = "emmcex_oe";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		vin-supply = <&emmcex_3v3>;
		gpio = <&gpio1 14 0>;
		startup-delay-us = <2000>;
		enable-active-low;
	};

	vsys_1v8: fixedregulator-vsys1v8 {
		/* Output 2 of TPS43351QDAPRQ1 on dra72-evm */
		/* Output 2 of LM5140QRWGTQ1 on dra71-evm */
		compatible = "regulator-fixed";
		regulator-name = "vsys_1v8";
		regulator-min-microvolt = <1800000>;
		regulator-max-microvolt = <1800000>;
		vin-supply = <&evm_12v0>;
		regulator-always-on;
		regulator-boot-on;
	};


	vmmcwl_fixed: fixedregulator-mmcwl {
		compatible = "regulator-fixed";
		regulator-name = "vmmcwl_fixed";
		regulator-min-microvolt = <1800000>;
		regulator-max-microvolt = <1800000>;
		gpio = <&gpio4 7 0>;
		startup-delay-us = <70000>;
		enable-active-high;
		vin-supply = <&evm_12v0>;
		//regulator-always-on;
		//regulator-boot-on;
	};


    extcon_usb1: extcon_usb1 {
        compatible = "linux,extcon-usb-gpio";
        //id-gpio = <&gpio2 24 GPIO_ACTIVE_HIGH>;
        vbus-gpio = <&gpio6 12 GPIO_ACTIVE_HIGH>;
     };

    extcon_usb2: extcon_usb2 {
        compatible = "linux,extcon-usb-gpio";
        id-gpio = <&gpio2 25 GPIO_ACTIVE_HIGH>;
        //vbus-gpio = <&gpio6 13 GPIO_ACTIVE_HIGH>;
     };

	reserved-memory {
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

        cmem_block_mem_0: cmem_block_mem@a0000000 {
          reg = <0x0 0xa0000000 0x0 0x0c000000>;
          no-map;
          status = "okay";
        };

		ipu2_cma_pool: ipu2_cma@95800000 {
			compatible = "shared-dma-pool";
			reg = <0x0 0x95800000 0x0 0x3800000>;
			reusable;
			status = "okay";
		};

		dsp1_cma_pool: dsp1_cma@99000000 {
			compatible = "shared-dma-pool";
			reg = <0x0 0x99000000 0x0 0x4000000>;
			reusable;
			status = "okay";
		};

		ipu1_cma_pool: ipu1_cma@9d000000 {
			compatible = "shared-dma-pool";
			reg = <0x0 0x9d000000 0x0 0x2000000>;
			reusable;
			status = "okay";
		};
	};

    cmem {
        compatible = "ti,cmem";
        #address-cells = <1>;
        #size-cells = <0>;

        #pool-size-cells = <2>;

        status = "okay";

        cmem_block_0: cmem_block@0 {
            reg = <0>;
            memory-region = <&cmem_block_mem_0>;
            cmem-buf-pools = <1 0x0 0x0c000000>;
        };
    };
    gpio-keys {
        compatible = "gpio-keys";
        autorepeat;

		set {
			label = "Key_set";
			linux,code = <103>;
			gpios = <&gpio4 3 GPIO_ACTIVE_LOW>;
		};

		ok {
			label = "Key_ok";
			linux,code = <104>;
			gpios = <&gpio4 4 GPIO_ACTIVE_LOW>;
		};
		emmc {
			label = "Key_emmc";
			linux,code = <105>;
			gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
		};
    };
	leds {
		compatible = "gpio-leds";
		/*wdt-led {
			label = "wdt";
			gpios = <&gpio6 11 GPIO_ACTIVE_LOW>;
			default-state = "on";
			linux,default-trigger = "heartbeat";
		};*/


		h41-led {
			label = "h41";
			gpios = <&gpio4 8 GPIO_ACTIVE_HIGH>;
			default-state = "off";
			linux,default-trigger = "none";
		};

		h42-led {
			label = "h42";
			gpios = <&gpio4 9 GPIO_ACTIVE_HIGH>;
			default-state = "off";
			linux,default-trigger = "none";
		};

		h43-led {
			label = "h43";
			gpios = <&gpio4 11 GPIO_ACTIVE_HIGH>;
			default-state = "off";
			linux,default-trigger = "none";
		};

		h44-led {
			label = "h44";
			gpios = <&gpio4 12 GPIO_ACTIVE_HIGH>;
			default-state = "off";
			linux,default-trigger = "none";
		};

		h51-led {
			label = "h51";
			gpios = <&gpio5 4 GPIO_ACTIVE_HIGH>;
			default-state = "on";
			linux,default-trigger = "none";
		};

		h52-led {
			label = "h52";
			gpios = <&gpio6 7 GPIO_ACTIVE_HIGH>;
			default-state = "on";
			linux,default-trigger = "heartbeat";
		};

		h53-led {
			label = "h53";
			gpios = <&gpio6 14 GPIO_ACTIVE_HIGH>;
			default-state = "off";
			linux,default-trigger = "mmc2";
		};

		h54-led {
			label = "h54";
			gpios = <&gpio6 15 GPIO_ACTIVE_HIGH>;
			default-state = "off";
			linux,default-trigger = "none";
		};

		h61-led {
			label = "h61";
			gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>;
			default-state = "off";
			linux,default-trigger = "none";
		};

		h62-led {
			label = "h62";
			gpios = <&gpio3 29 GPIO_ACTIVE_HIGH>;
			default-state = "off";
			linux,default-trigger = "none";
		};

		h63-led {
			label = "h63";
			gpios = <&gpio7 23 GPIO_ACTIVE_HIGH>;
			default-state = "off";
			linux,default-trigger = "none";
		};

		h64-led {
			label = "h64";
			gpios = <&gpio7 31 GPIO_ACTIVE_HIGH>;
			default-state = "off";
			linux,default-trigger = "none";
		};
	};

	/* Dual mac ethernet application node on icss2 */
	pruss1_eth: pruss1_eth {
		status = "okay";
		compatible = "ti,am57-prueth";
		pruss = <&pruss1>;
		sram = <&ocmcram1>;
		interrupt-parent = <&pruss1_intc>;

		pruss1_emac0: ethernet-mii0 {
			phy-handle = <&pruss1_eth0_phy>;
			phy-mode = "mii";
			interrupts = <20>, <22>;
			interrupt-names = "rx", "tx";
			/* Filled in by bootloader */
			local-mac-address = [00 00 00 00 00 00];
		};

		pruss1_emac1: ethernet-mii1 {
			phy-handle = <&pruss1_eth1_phy>;
			phy-mode = "mii";
			interrupts = <21>, <23>;
			interrupt-names = "rx", "tx";
			/* Filled in by bootloader */
			local-mac-address = [00 00 00 00 00 00];
		};
	};
	sound0: sound@0 {
		compatible = "simple-audio-card";
		simple-audio-card,name = "DRA7xx-EVM";
		simple-audio-card,format = "i2s";
		//simple-audio-card,mclk-fs = <128>;
		simple-audio-card,bitclock-master = <&sound_master>;
		simple-audio-card,frame-master = <&sound_master>;
		simple-audio-card,widgets =
			"Headphone", "Headphone Jack",
			"Line", "Line In";
		simple-audio-card,routing =
			"Headphone Jack",	"SPK_LP",
			"Headphone Jack",	"SPK_RP",
			"LINPUT1",		"Line In",
			"RINPUT1",		"Line In";

		dailink0_master: simple-audio-card,cpu {
			sound-dai = <&mcasp4>;
		};

		sound_master: simple-audio-card,codec {
			sound-dai = <&tlv320aic34_a>;
			system-clock-frequency = <12000000>;
		};
	};
};


&cpu0_opp_table {
       opp_500@500000000 {
               opp-hz = /bits/ 64 <500000000>;
               opp-microvolt = <1060000 850000 1150000>,
                       <1060000 850000 1150000>;
               opp-supported-hw = <0xFF 0x01>;
       };
       opp_200@200000000 {
               opp-hz = /bits/ 64 <200000000>;
               opp-microvolt = <1060000 850000 1150000>,
                       <1060000 850000 1150000>;
               opp-supported-hw = <0xFF 0x01>;
       };

        /delete-node/ opp_od@1176000000;
        /delete-node/ opp_high@1500000000;
      
};

&mac {
	status = "okay";
	//dual_emac;
};

&phy_sel {
	rmii-clock-ext;
};

&cpsw_emac0 {
	phy_id = <&davinci_mdio>, <3>;
};

&cpsw_emac1 {
	phy_id = <&davinci_mdio>, <0>;
};

&davinci_mdio {
	pinctrl-names = "default", "sleep";
	pinctrl-0 = <&davinci_mdio_pins_default>;
	pinctrl-1 = <&davinci_mdio_pins_sleep>;
};

&i2c1 {
	status = "okay";

	lp8733: lp8733@60 {
		compatible = "ti,lp8733";
		reg = <0x60>;

		buck0-in-supply =<&vsys_3v3>;
		buck1-in-supply =<&vsys_3v3>;
		ldo0-in-supply =<&evm_5v0>;
		ldo1-in-supply =<&evm_5v0>;

		lp8733_regulators: regulators {
			lp8733_buck0_reg: buck0 {
				/* FB_B0 -> LP8733-BUCK1 - VPO_S1_AVS - VDD_CORE_AVS (core, mpu, gpu) */
				regulator-name = "lp8733-buck0";
				regulator-min-microvolt = <850000>;
				regulator-max-microvolt = <1250000>;
				regulator-always-on;
				regulator-boot-on;
			};

			lp8733_buck1_reg: buck1 {
				/* FB_B1 -> LP8733-BUCK2 - VPO_S2_AVS - VDD_DSP_AVS (DSP/eve/iva) */
				regulator-name = "lp8733-buck1";
				regulator-min-microvolt = <850000>;
				regulator-max-microvolt = <1250000>;
				regulator-boot-on;
				regulator-always-on;
			};

			lp8733_ldo0_reg: ldo0 {
				/* LDO0 -> LP8733-LDO1 - VPO_L1_3V3 - VDDSHV8 (optional) */
				regulator-name = "lp8733-ldo0";
				regulator-min-microvolt = <3300000>;
				regulator-max-microvolt = <3300000>;
				regulator-boot-on;
				regulator-always-on;
			};

			lp8733_ldo1_reg: ldo1 {
				/* LDO1 -> LP8733-LDO2 - VPO_L2_3V3 - VDDA_USB3V3 */
				regulator-name = "lp8733-ldo1";
				regulator-min-microvolt = <3300000>;
				regulator-max-microvolt = <3300000>;
				regulator-always-on;
				regulator-boot-on;
			};
		};
	};

	lp8732: lp8732@61 {
		compatible = "ti,lp8732";
		reg = <0x61>;

		buck0-in-supply =<&vsys_3v3>;
		buck1-in-supply =<&vsys_3v3>;
		ldo0-in-supply =<&vsys_3v3>;
		ldo1-in-supply =<&vsys_3v3>;

		lp8732_regulators: regulators {
			lp8732_buck0_reg: buck0 {
				/* FB_B0 -> LP8732-BUCK1 - VPO_S3_1V8 - VDDS_1V8 */
				regulator-name = "lp8732-buck0";
				regulator-min-microvolt = <1800000>;
				regulator-max-microvolt = <1800000>;
				regulator-always-on;
				regulator-boot-on;
			};

			lp8732_buck1_reg: buck1 {
				/* FB_B1 -> LP8732-BUCK2 - VPO_S4_DDR - VDD_DDR_1V35 */
				regulator-name = "lp8732-buck1";
				regulator-min-microvolt = <1350000>;
				regulator-max-microvolt = <1350000>;
				regulator-boot-on;
				regulator-always-on;
			};

			lp8732_ldo0_reg: ldo0 {
				/* LDO0 -> LP8732-LDO1 - VPO_L3_1V8 - VDA_1V8_PLL */
				regulator-name = "lp8732-ldo0";
				regulator-min-microvolt = <1800000>;
				regulator-max-microvolt = <1800000>;
				regulator-boot-on;
				regulator-always-on;
			};

			lp8732_ldo1_reg: ldo1 {
				/* LDO1 -> LP8732-LDO2 - VPO_L4_1V8 - VDA_1V8_PHY */
				regulator-name = "lp8732-ldo1";
				regulator-min-microvolt = <1800000>;
				regulator-max-microvolt = <1800000>;
				regulator-always-on;
				regulator-boot-on;
			};
		};
	};

    	rtc_pcf8563: rtc@51 {
            compatible = "nxp,pcf8563";
            reg = <0x51>;
	    status = "disable";
            interrupt-parent = <&gpio6>;
            interrupts = <16 IRQ_TYPE_EDGE_FALLING>;
        };

        /delete-node/ tc358778@0e;
        /delete-node/ tpic2810@60;
    	tps659038@58 {
           /delete-node/ tps659038_usb;
        };
	ov2659@30 {
	    status = "disabled";
	};
        PCM1862: PCM1860@4a {

        compatible = "ti,pcm18xx";
             reg = <0x4a>;
        };
        PCM1863: PCM1861@4b {
        compatible = "ti,pcm18xx";
            reg = <0x4b>;
        };
        is31fl3236: led-controller@3c {
	        compatible = "issi,is31fl3236";
	        reg = <0x3c>;
	        #address-cells = <1>;
	        #size-cells = <0>;

	        led@1 {
		       reg = <1>;
		       label = "AngelLed";
               linux,default-trigger = "default-off";
	        };
        };

        lkt4106: lkt4106@28 {
        compatible = "lkt4106";
             reg = <0x28>;
        };

        rv3028: rv3028@52 {
		compatible = "microcrystal,rv3028";
		reg = <0x52>;
		interrupt-parent = <&gpio1>;
		interrupts = <0 IRQ_TYPE_EDGE_FALLING>;
        };
};


&i2c3 {
	pinctrl-names = "default";
	pinctrl-0 = <&i2c3_pins_default>;

	clock-frequency = <400000>;
	status = "okay";
	wm8960: wm8960@1a {
		#sound-dai-cells = <0>;
        compatible = "wlf,wm8960";
        reg = <0x1a>;
        wlf,shared-lrclk;

       };
	eeprom_core: eeprom_core@50 {
        compatible = "atmel,24c256";
        reg = <0x50>;
        pagesize = <32>;
        status = "okay";
		     };

};

/*
&i2c4 {
	status = "okay";
	clock-frequency = <400000>;

	pinctrl-names = "default";
	pinctrl-0 = <&i2c4_pins_default>;

        PCM1860: PCM1860@4a {

        compatible = "ti,pcm18xx";
           reg = <0x4a>;
        };
        PCM1861: PCM1861@4b {
        compatible = "ti,pcm18xx";
        reg = <0x4b>;
        };
        AIC31: AIC31@1b {
         compatible = "ti,AIC31XX";
               reg = <0x1b>;
        };
        AIC31_2: AIC31@18 {
         compatible = "ti,AIC31XX";
               reg = <0x18>;
        };

};
*/
&i2c4 {
	status = "okay";
	clock-frequency = <400000>;

	pinctrl-names = "default";
	pinctrl-0 = <&i2c4_pins_default>;

	 tlv320aic34_a: tlv320aic34_a@1a {
                #sound-dai-cells = <0>;
                compatible = "ti,tlv320aic3x";
                reg = <0x1a>;
                adc-settle-ms = <40>;
                ai3x-micbias-vg = <1>;
                status = "disabled";

                AVDD-supply = <&vsys_3v3>;
                IOVDD-supply = <&vsys_3v3>;
                DRVDD-supply = <&vsys_3v3>;
		DVDD-supply = <&vsys_1v8>;
        };
	aic34_1@1a {
        compatible = "ti,aic3x";
        reg  = <0x1a>;
  
    };
    aic34_2@1b {
        compatible = "ti,aic3x";
        reg = <0x1b>;
    };
  
  
    mcp4441@2d {
	status = "disabled";
    	compatible = "microchip,mcp4441-103";
        reg = <0x2d>;
        gpio-addr-a0 = <&gpio2 29 GPIO_ACTIVE_LOW>;
    };

    ds1881_1@28 {
    	compatible = "maxim,ds1881-045";
        reg = <0x28>;
        enable-gpios = <&gpio2 29 GPIO_ACTIVE_LOW>;
    };

    /* PCM1860: PCM1860@4a {

        compatible = "ti,pcm18xx";
           reg = <0x4a>;
     };
        PCM1861: PCM1861@4b {
        compatible = "ti,pcm18xx";
        reg = <0x4b>;
        };
        AIC31: AIC31@1b {
         compatible = "ti,AIC31XX";
               reg = <0x1b>;
        };
        AIC31_2: AIC31@18 {
         compatible = "ti,AIC31XX";
               reg = <0x18>;
        };
     */
	/*hy461x@38 {
		compatible = "qcom,hy461x";
		reg = <0x38>;
		//pinctrl-names = "default";
		//pinctrl-0 = <&tp_pin>;

		qcom,ts-gpio-reset = <&gpio2 2 GPIO_ACTIVE_HIGH>;
		qcom,ts-gpio-irq = <&gpio2 27 GPIO_ACTIVE_HIGH>;

		qcom,max-x = <1024>;
		qcom,max-y = <600>;
		qcom,hard-reset-delay-ms = <220>;
		qcom,soft-reset-delay-ms = <220>;
	};

	goodix_ts@5d {
		compatible = "goodix,gt9xx";
		reg = <0x5d>;
		goodix,irq-gpio = <&gpio2 27 IRQ_TYPE_EDGE_RISING>;
		goodix,rst-gpio = <&gpio2 2 GPIO_ACTIVE_LOW>;
		goodix,cfg-group2 = [
00 00 05 20 03 05 0D 00 01 C8 28 0F 50 32 03 05 00 00 00 00 00 00 00 00 00 00 00 90 30 AA 20 1E 0C 08 00 00 00 9A 02 2D 00 00 00 00 00 00 00 00 00 00 00 0F 2D 94 C5 02 07 00 00 04 E0 10 00 B8 14 00 92 1A 00 7A 20 00 65 28 00 64 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 19 18 17 16 15 14 11 10 0F 0E 0D 0C 09 08 07 06 05 04 01 00 00 00 00 00 00 00 00 00 00 00 2A 29 28 27 26 25 24 23 22 21 20 1F 1E 1C 1B 19 14 13 12 11 10 0F 0E 0D 0C 0A 08 07 06 04 02 00 00 00 00 00 00 00 00 00 00 00 43 01
		];
	};

	tlv320aic3106: tlv320aic3106@1b {
		#sound-dai-cells = <0>;
		compatible = "ti,tlv320aic3106";
		reg = <0x1b>;
		adc-settle-ms = <40>;
		ai3x-micbias-vg = <1>;
		assigned-clocks = <&clkoutmux2_clk_mux>;
		assigned-clock-parents = <&sys_clk2_dclk_div>;
		status = "okay";
		gpio-reset = <&gpio5 14 GPIO_ACTIVE_HIGH>;

		AVDD-supply = <&vsys_3v3>;
		IOVDD-supply = <&vsys_3v3>;
		DRVDD-supply = <&vsys_3v3>;
		DVDD-supply = <&vsys_1v8>;
	};
	tlv320aic3106: tlv320aic3106@18 {
		#sound-dai-cells = <0>;
		compatible = "ti,tlv320aic3106";
		reg = <0x18>;
		adc-settle-ms = <40>;
		ai3x-micbias-vg = <1>;		
		assigned-clocks = <&clkoutmux2_clk_mux>;
		assigned-clock-parents = <&sys_clk2_dclk_div>;
		status = "okay";

		AVDD-supply = <&vsys_3v3>;
		IOVDD-supply = <&vsys_3v3>;
		DRVDD-supply = <&vsys_3v3>;
		DVDD-supply = <&vsys_1v8>;
	};
	gpio_csi2_adap: tca6416@20 {
		status = "okay";
		compatible = "ti,tca6416";
		reg = <0x20>;
		gpio-controller;
		#gpio-cells = <2>;
	};

	ov490@36 {
		compatible = "ovti,ov490";
		reg = <0x36>;

		mux-gpios = <&gpio_csi2_adap 0	GPIO_ACTIVE_LOW>,
			    <&gpio_csi2_adap 1	GPIO_ACTIVE_HIGH>,
			    <&gpio_csi2_adap 3	GPIO_ACTIVE_HIGH>,
			    <&gpio_csi2_adap 4	GPIO_ACTIVE_LOW>;
		port {
			csi2_cam0: endpoint@0 {
				clock-lanes = <0>;
				data-lanes = <1 2>;
				remote-endpoint = <&csi2_phy0>;
			};
		};
	};
*/

	tmp112: tmp112@48 {
		compatible = "ti,tmp102";
		reg = <0x48>;
	};
};

&mcspi1 {
	pinctrl-names = "default";
	pinctrl-0 = <&mcspi1_pins_default>;
	status = "okay";
	ti,pindir-d0-out-d1-in;
	ti,spi-num-cs = <1>;

/*
	spidev1: spi@0 {
		compatible = "rohm,dh2228fv";
		reg = <0>;
		spi-max-frequency = <500000>;
	};
*/
	 hi3599@0 {
		 compatible = "hi,hi3599";
		 reg = <0>;
		 interrupt-parent = <&gpio7>;
		 interrupts = <11 0>;
		 irq-gpio = <&gpio7 11 0>;
		 spi-max-frequency = <5000000>;
	 };
};

&mcspi2 {
	pinctrl-names = "default";
	pinctrl-0 = <&mcspi2_pins_default>;
	status = "okay";
	ti,pindir-d0-out-d1-in;
	ti,spi-num-cs = <1>;

/*
	spidev2: spi@0 {
		compatible = "rohm,dh2228fv";
		reg = <0>;
		spi-max-frequency = <500000>;
	};
*/
	 hi8429@0 {
		 compatible = "hi,hi8429";
		 reg = <0>;
		 interrupt-parent = <&gpio5>;
		 interrupts = <6 0>;
		 irq-gpio = <&gpio5 6 0>;
		 rst-gpio = <&gpio5 7 0>;
		 sel0-gpio = <&gpio5 9 0>;
		 sel1-gpio = <&gpio5 8 0>;
		 spi-max-frequency = <5000000>;
	 };
};

&uart1 {
    compatible = "ti,omap2-uart";
	pinctrl-names = "default";
    status = "disabled";
	pinctrl-0 = <&uart1_pins_default>;

    /* GPIO7 pin 25 for data direction */
    //rts-gpio = <&gpio7 25 GPIO_ACTIVE_HIGH>;
    //rs485-rts-active-high;
    //rs485-rts-delay = <1 1>;      /* in milliseconds */
    //linux,rs485-enabled-at-boot-time;
};

&uart6 {
     pinctrl-names = "default";
     status = "disabled";
};
&uart10 {
	pinctrl-names = "default";
	pinctrl-0 = <&uart10_pins_default>;

	status = "disabled";
};



&mcspi3 {
	status = "disabled";
};

&atl {
	assigned-clocks = <&abe_dpll_sys_clk_mux>,
			  <&atl_gfclk_mux>,
			  <&dpll_abe_ck>,
			  <&dpll_abe_m2x2_ck>,
			  <&atl_clkin2_ck>;
	assigned-clock-parents = <&sys_clkin2>, <&dpll_abe_m2_ck>;
	//assigned-clock-rates = <0>, <0>, <180633600>, <361267200>, <5644800>;
	assigned-clock-rates = <0>, <0>, <180633600>, <361267200>, <11289600>;

	status = "okay";

	atl2 {
		bws = <DRA7_ATL_WS_MCASP2_FSX>;
		aws = <DRA7_ATL_WS_MCASP3_FSX>;
	};
};

&mcasp4 {
	#sound-dai-cells = <0>;

	assigned-clocks = <&mcasp4_ahclkx_mux>;
	assigned-clock-parents = <&atl_clkin2_ck>;

	pinctrl-names = "default", "sleep";
	pinctrl-0 = <&mcasp4_pins_default>;
	pinctrl-1 = <&mcasp4_pins_sleep>;
	status = "disabled";

	op-mode = <0>;	/* MCASP_IIS_MODE */
	tdm-slots = <2>;
	/* 4 serializers */
	serial-dir = <	/* 0: INACTIVE, 1: TX, 2: RX */
		1 0 0 0
	>;
	tx-num-evt = <32>;
	rx-num-evt = <32>;
};

&mcasp2 {
	status = "disabled";
	#sound-dai-cells = <0>;

	assigned-clocks = <&mcasp2_ahclkx_mux>;
	assigned-clock-parents = <&sys_clkin2>;

	pinctrl-names = "default";
	pinctrl-0 = <&mcasp2_pins_default>;
	

	op-mode = <0>;	/* MCASP_IIS_MODE */
	tdm-slots = <2>;
	/* 4 serializers */
	serial-dir = <	/* 0: INACTIVE, 1: TX, 2: RX */
		1 2 0 0
		/*1 2 1 2*/
		/*0 0 1 2*/
	>;
	tx-num-evt = <32>;
	rx-num-evt = <32>;
};

&mcasp5 {
	status = "disable";
	#sound-dai-cells = <0>;
	pinctrl-names = "default", "sleep";
	pinctrl-0 = <&mcasp5_pins_default>;
	pinctrl-1 = <&mcasp5_pins_sleep>;

	op-mode = <0>;	/* MCASP_IIS_MODE */
	tdm-slots = <2>;
	/* 4 serializers */
	serial-dir = <	/* 0: INACTIVE, 1: TX, 2: RX */
		1 2 0 0
	>;
	tx-num-evt = <32>;
	rx-num-evt = <32>;
};

&mcasp6 {
	status = "disable";
	#sound-dai-cells = <0>;

	assigned-clocks = <&mcasp6_ahclkx_mux>;
	assigned-clock-parents = <&atl_clkin2_ck>;

	pinctrl-names = "default", "sleep";
	pinctrl-0 = <&mcasp6_pins_default>;
	pinctrl-1 = <&mcasp6_pins_sleep>;

	op-mode = <0>;	/* MCASP_IIS_MODE */
	tdm-slots = <2>;
	/* 4 serializers */
	serial-dir = <	/* 0: INACTIVE, 1: TX, 2: RX */
		1 2 0 0
	>;
	tx-num-evt = <32>;
	rx-num-evt = <32>;
};

&dra7_pmx_core {
	pinctrl-names = "default";
	pinctrl-0 = <&board_pins>;

	board_pins: pinmux_board_pins {
		pinctrl-single,pins = <

			DRA7XX_CORE_IOPAD(0x3724, 0x200e) /*gpio5_13 */
			DRA7XX_CORE_IOPAD(0x34c8, 0x6000e) /*gpio2_24 usb1 id*/  
			DRA7XX_CORE_IOPAD(0x34cc, 0x6000e) /*gpio2_25 usb2 id*/ 
			DRA7XX_CORE_IOPAD(0x3680, 0x90000)/* usb drv */
			DRA7XX_CORE_IOPAD(0x3680, 0xa000e)/* usb drv */
			DRA7XX_CORE_IOPAD(0x371c, 0x4000e) /*gpio2_29 hp det*/

			DRA7XX_CORE_IOPAD(0x37bc, 0x2000e)	/* gpio7_13 wifi wl-reg-on */ 
			DRA7XX_CORE_IOPAD(0x3728, 0x8000e) /* gpio5_14 spk sdn*/
			DRA7XX_CORE_IOPAD(0x3778, 0x20000) /* gpio6_11 camera pwdn*/

			DRA7XX_CORE_IOPAD(0x3774, 0x20000)/* gpio6_10 wdt_enable */
			DRA7XX_CORE_IOPAD(0x3778, 0x20000)/* gpio6_11 wdt_feed */
			DRA7XX_CORE_IOPAD(0x3714, 0x6000e)/* gpio1_4 power_down */
			DRA7XX_CORE_IOPAD(0x36c0, 0x6000e)/* gpio5_5 power_fault */
			DRA7XX_CORE_IOPAD(0x3720, 0x2000e)/* gpio1_5 pwr_4g */
			DRA7XX_CORE_IOPAD(0x3684, 0x8000e)/* gpio6_13 pwr_wifi pull_down*/
			DRA7XX_CORE_IOPAD(0x3580, 0x0000e)/* gpio4_7 wl_en */
			DRA7XX_CORE_IOPAD(0x3584, 0x0000e)/* gpio4_8 h4 */
			DRA7XX_CORE_IOPAD(0x3588, 0x0000e)/* gpio4_9 h4 */
			DRA7XX_CORE_IOPAD(0x3590, 0x0000e)/* gpio4_11 h4 */
			DRA7XX_CORE_IOPAD(0x3594, 0x0000e)/* gpio4_12 h4 */
			DRA7XX_CORE_IOPAD(0x36bc, 0x0000e)/* gpio5_4 h5 */
			DRA7XX_CORE_IOPAD(0x3718, 0x0000e)/* gpio6_7 h5 */
			DRA7XX_CORE_IOPAD(0x3688, 0x00000)/* gpio6_14 h5 */
			DRA7XX_CORE_IOPAD(0x368c, 0x00000)/* gpio6_15 h5 */
			DRA7XX_CORE_IOPAD(0x3470, 0x0000e)/* gpio2_2 h6 */
			DRA7XX_CORE_IOPAD(0x3558, 0x0000e)/* gpio3_29 h6 */
			DRA7XX_CORE_IOPAD(0x37e4, 0x0000e)/* gpio7_23 h6 */
			DRA7XX_CORE_IOPAD(0x36a4, 0x0000e)/* gpio7_31 h6 */
			DRA7XX_CORE_IOPAD(0x3560, 0x2000e)/* gpio3_31 sim_switch*/
			DRA7XX_CORE_IOPAD(0x3564, 0x0000e)/* gpio4_0 pwr_on_off*/
			DRA7XX_CORE_IOPAD(0x3568, 0x1000e)/* gpio4_1 rf_switch*/
			DRA7XX_CORE_IOPAD(0x356c, 0x1000e)/* gpio4_2 4g reset*/
			DRA7XX_CORE_IOPAD(0x3570, 0x6000e)/* gpio4_3 key s3*/
			DRA7XX_CORE_IOPAD(0x3574, 0x6000e)/* gpio4_4 key s2*/
			DRA7XX_CORE_IOPAD(0x37d0, 0x8000e)/* ext emmc enable dcan1_tx.gpio1_14 */
			DRA7XX_CORE_IOPAD(0x3578, 0x0000e)/* gpio4_5 ext emmc pwr pull down*/
			DRA7XX_CORE_IOPAD(0x3818, 0x6000e)/* gpio1_0 rtc int */
			DRA7XX_CORE_IOPAD(0x37d4, 0xe000e)/* gpio1_15 ext emmc key */
			DRA7XX_CORE_IOPAD(0x36c4, 0x5000e)/* gpio5_6 hi8429 int */
			DRA7XX_CORE_IOPAD(0x36c8, 0x1000e)/* gpio5_7 hi8429 rstn */
			DRA7XX_CORE_IOPAD(0x36cc, 0x1000e)/* gpio5_8 hi8429 sel0 */
			DRA7XX_CORE_IOPAD(0x36d0, 0x1000e)/* gpio5_9 hi8429 sel1 */
			DRA7XX_CORE_IOPAD(0x3644, 0x6000e) /*wl int gpio5_17*/
			DRA7XX_CORE_IOPAD(0x371c, 0xa000e) /* gpio2_29 a0 pin*/
			DRA7XX_CORE_IOPAD(0x3690, 0x10000) /* gpio6_16 */
			DRA7XX_CORE_IOPAD(0x369c, 0x1000e) /* gpio6_19 */
		>;
	};

	mmc1_pins_default: mmc1_pins_default {
		pinctrl-single,pins = <
			DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
			DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
			DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
			DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
			DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */
			DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */
			DRA7XX_CORE_IOPAD(0x376c, 0xd000e) /* mmc1_sdcd.gpio6_27 */
			DRA7XX_CORE_IOPAD(0x3770, 0xd000e) /* mmc1_sdwp.gpio6_28 */
		>;
	};

	mmc1_pins_hs: mmc1_pins_hs {
		pinctrl-single,pins = <
			DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
			DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
			DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
			DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
			DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */
			DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */
			DRA7XX_CORE_IOPAD(0x376c, 0xd000e) /* mmc1_sdcd.gpio6_27 */
			DRA7XX_CORE_IOPAD(0x3770, 0xd000e) /* mmc1_sdwp.gpio6_28 */
		>;
	};

	mmc2_pins_default: mmc2_pins_default {
		pinctrl-single,pins = <
			DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */
			DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
			DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
			DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
			DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
			DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
			DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
			DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
			DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
			DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
		>;
	};

	mmc2_pins_hs: mmc2_pins_hs {
		pinctrl-single,pins = <
			DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */
			DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
			DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
			DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
			DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
			DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
			DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
			DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
			DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
			DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
		>;
	};

	mmc2_pins_ddr_1_8v: mmc2_pins_ddr_1_8v {
		pinctrl-single,pins = <
			DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a23.mmc2_clk */
			DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
			DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
			DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
			DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
			DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
			DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
			DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
			DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
			DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
		>;
	};

	mmc3_pins_ds: pinmux_mmc3_pins_ds {
		pinctrl-single,pins = <
			DRA7XX_CORE_IOPAD(0x377c, PIN_INPUT_PULLUP | MUX_MODE0) 	/* mmc3_clk.mmc3_clk */
			DRA7XX_CORE_IOPAD(0x3780, PIN_INPUT_PULLUP | MUX_MODE0) 	/* mmc3_cmd.mmc3_cmd */
			DRA7XX_CORE_IOPAD(0x3784, PIN_INPUT_PULLUP | MUX_MODE0) 	/* mmc3_dat0.mmc3_dat0 */
			DRA7XX_CORE_IOPAD(0x3788, PIN_INPUT_PULLUP | MUX_MODE0) 	/* mmc3_dat1.mmc3_dat1 */
			DRA7XX_CORE_IOPAD(0x378c, PIN_INPUT_PULLUP | MUX_MODE0) 	/* mmc3_dat2.mmc3_dat2 */
			DRA7XX_CORE_IOPAD(0x3790, PIN_INPUT_PULLUP | MUX_MODE0) 	/* mmc3_dat3.mmc3_dat3 */
			DRA7XX_CORE_IOPAD(0x3794, PIN_INPUT_PULLUP | MUX_MODE0) 	/* mmc3_dat4.mmc3_dat4 */
			DRA7XX_CORE_IOPAD(0x3798, PIN_INPUT_PULLUP | MUX_MODE0) 	/* mmc3_dat5.mmc3_dat5 */
			DRA7XX_CORE_IOPAD(0x379c, PIN_INPUT_PULLUP | MUX_MODE0) 	/* mmc3_dat6.mmc3_dat6 */
			DRA7XX_CORE_IOPAD(0x37a0, PIN_INPUT_PULLUP | MUX_MODE0) 	/* mmc3_dat7.mmc3_dat7 */
		>;
	};

	mmc3_pins_sdr12: pinmux_mmc3_pins_sdr12 {
		pinctrl-single,pins = <
			DRA7XX_CORE_IOPAD(0x377c, PIN_INPUT_PULLUP | MUX_MODE0) 	/* mmc3_clk.mmc3_clk */
			DRA7XX_CORE_IOPAD(0x3780, PIN_INPUT_PULLUP | MUX_MODE0) 	/* mmc3_cmd.mmc3_cmd */
			DRA7XX_CORE_IOPAD(0x3784, PIN_INPUT_PULLUP | MUX_MODE0) 	/* mmc3_dat0.mmc3_dat0 */
			DRA7XX_CORE_IOPAD(0x3788, PIN_INPUT_PULLUP | MUX_MODE0) 	/* mmc3_dat1.mmc3_dat1 */
			DRA7XX_CORE_IOPAD(0x378c, PIN_INPUT_PULLUP | MUX_MODE0) 	/* mmc3_dat2.mmc3_dat2 */
			DRA7XX_CORE_IOPAD(0x3790, PIN_INPUT_PULLUP | MUX_MODE0) 	/* mmc3_dat3.mmc3_dat3 */
		>;
	};

	mmc3_pins_hs: pinmux_mmc3_pins_hs {
		pinctrl-single,pins = <
			DRA7XX_CORE_IOPAD(0x377c, PIN_INPUT_PULLUP | MUX_MODE0) 	/* mmc3_clk.mmc3_clk */
			DRA7XX_CORE_IOPAD(0x3780, PIN_INPUT_PULLUP | MUX_MODE0) 	/* mmc3_cmd.mmc3_cmd */
			DRA7XX_CORE_IOPAD(0x3784, PIN_INPUT_PULLUP | MUX_MODE0) 	/* mmc3_dat0.mmc3_dat0 */
			DRA7XX_CORE_IOPAD(0x3788, PIN_INPUT_PULLUP | MUX_MODE0) 	/* mmc3_dat1.mmc3_dat1 */
			DRA7XX_CORE_IOPAD(0x378c, PIN_INPUT_PULLUP | MUX_MODE0) 	/* mmc3_dat2.mmc3_dat2 */
			DRA7XX_CORE_IOPAD(0x3790, PIN_INPUT_PULLUP | MUX_MODE0) 	/* mmc3_dat3.mmc3_dat3 */
		>;
	};

	mmc3_pins_sdr25: pinmux_mmc3_pins_sdr25 {
		pinctrl-single,pins = <
			DRA7XX_CORE_IOPAD(0x377c, PIN_INPUT_PULLUP | MUX_MODE0) 	/* mmc3_clk.mmc3_clk */
			DRA7XX_CORE_IOPAD(0x3780, PIN_INPUT_PULLUP | MUX_MODE0) 	/* mmc3_cmd.mmc3_cmd */
			DRA7XX_CORE_IOPAD(0x3784, PIN_INPUT_PULLUP | MUX_MODE0) 	/* mmc3_dat0.mmc3_dat0 */
			DRA7XX_CORE_IOPAD(0x3788, PIN_INPUT_PULLUP | MUX_MODE0) 	/* mmc3_dat1.mmc3_dat1 */
			DRA7XX_CORE_IOPAD(0x378c, PIN_INPUT_PULLUP | MUX_MODE0) 	/* mmc3_dat2.mmc3_dat2 */
			DRA7XX_CORE_IOPAD(0x3790, PIN_INPUT_PULLUP | MUX_MODE0) 	/* mmc3_dat3.mmc3_dat3 */
		>;
	};

	mmc3_pins_sdr50: pinmux_mmc3_pins_sdr50 {
		pinctrl-single,pins = <
			DRA7XX_CORE_IOPAD(0x377c, PIN_INPUT_PULLUP | 1<<8 | MUX_MODE0) 	/* mmc3_clk.mmc3_clk */
			DRA7XX_CORE_IOPAD(0x3780, PIN_INPUT_PULLUP | 1<<8 | MUX_MODE0) 	/* mmc3_cmd.mmc3_cmd */
			DRA7XX_CORE_IOPAD(0x3784, PIN_INPUT_PULLUP | 1<<8 | MUX_MODE0) 	/* mmc3_dat0.mmc3_dat0 */
			DRA7XX_CORE_IOPAD(0x3788, PIN_INPUT_PULLUP | 1<<8 | MUX_MODE0) 	/* mmc3_dat1.mmc3_dat1 */
			DRA7XX_CORE_IOPAD(0x378c, PIN_INPUT_PULLUP | 1<<8 | MUX_MODE0) 	/* mmc3_dat2.mmc3_dat2 */
			DRA7XX_CORE_IOPAD(0x3790, PIN_INPUT_PULLUP | 1<<8 | MUX_MODE0) 	/* mmc3_dat3.mmc3_dat3 */
		>;
	};

	vout3_ds: pinmux_vout3_ds {
		pinctrl-single,pins = <
			DRA7XX_CORE_IOPAD(0x3464, 0x90003)
			DRA7XX_CORE_IOPAD(0x3460, 0x90003)
			DRA7XX_CORE_IOPAD(0x34bc, 0x90003)
			DRA7XX_CORE_IOPAD(0x3468, 0x90003)
			DRA7XX_CORE_IOPAD(0x3400, 0x90003) /*d0*/
			DRA7XX_CORE_IOPAD(0x3404, 0x90003) /*d1*/
			DRA7XX_CORE_IOPAD(0x3408, 0x90003)
			DRA7XX_CORE_IOPAD(0x340c, 0x90003)
			DRA7XX_CORE_IOPAD(0x3410, 0x90003)
			DRA7XX_CORE_IOPAD(0x3414, 0x90003)
			DRA7XX_CORE_IOPAD(0x3418, 0x90003)
			DRA7XX_CORE_IOPAD(0x341c, 0x90003)
			DRA7XX_CORE_IOPAD(0x3420, 0x90003)
			DRA7XX_CORE_IOPAD(0x3424, 0x90003)
			DRA7XX_CORE_IOPAD(0x3428, 0x90003)
			DRA7XX_CORE_IOPAD(0x342c, 0x90003)
			DRA7XX_CORE_IOPAD(0x3430, 0x90003)
			DRA7XX_CORE_IOPAD(0x3434, 0x90003)
			DRA7XX_CORE_IOPAD(0x3438, 0x90003)
			DRA7XX_CORE_IOPAD(0x343c, 0x90003)
			DRA7XX_CORE_IOPAD(0x3440, 0x90003)
			DRA7XX_CORE_IOPAD(0x3444, 0x90003)
			DRA7XX_CORE_IOPAD(0x3448, 0x90003)
			DRA7XX_CORE_IOPAD(0x344c, 0x90003)
			DRA7XX_CORE_IOPAD(0x3450, 0x90003)
			DRA7XX_CORE_IOPAD(0x3454, 0x90003)
			DRA7XX_CORE_IOPAD(0x3458, 0x90003)
			DRA7XX_CORE_IOPAD(0x345c, 0x90003) /*d23*/


			DRA7XX_CORE_IOPAD(0x346c, 0x2000e)/* lcd pwr gpio2_1 */
		>;
	};
	vout2_ds: pinmux_vout2_ds {
		pinctrl-single,pins = <
			DRA7XX_CORE_IOPAD(0x3564, 0x90104)
			DRA7XX_CORE_IOPAD(0x3560, 0x90104)
			DRA7XX_CORE_IOPAD(0x355c, 0x90104)
			DRA7XX_CORE_IOPAD(0x3558, 0x90104)
			/*DRA7XX_CORE_IOPAD(0x3558, 0x2000e) de*/
			DRA7XX_CORE_IOPAD(0x35c4, 0x90104) /*d0*/
			DRA7XX_CORE_IOPAD(0x35c0, 0x90104) /*d1*/
			DRA7XX_CORE_IOPAD(0x35bc, 0x90104)
			DRA7XX_CORE_IOPAD(0x35b8, 0x90104)
			DRA7XX_CORE_IOPAD(0x35b4, 0x90104)
			DRA7XX_CORE_IOPAD(0x35b0, 0x90104)
			DRA7XX_CORE_IOPAD(0x35ac, 0x90104)
			DRA7XX_CORE_IOPAD(0x35a8, 0x90104)
			DRA7XX_CORE_IOPAD(0x35a4, 0x90104)
			DRA7XX_CORE_IOPAD(0x35a0, 0x90104)
			DRA7XX_CORE_IOPAD(0x359c, 0x90104)
			DRA7XX_CORE_IOPAD(0x3598, 0x90104)
			DRA7XX_CORE_IOPAD(0x3594, 0x90104)
			DRA7XX_CORE_IOPAD(0x3590, 0x90104)
			DRA7XX_CORE_IOPAD(0x358c, 0x90104)
			DRA7XX_CORE_IOPAD(0x3588, 0x90104)
			DRA7XX_CORE_IOPAD(0x3584, 0x90104)
			DRA7XX_CORE_IOPAD(0x3580, 0x90104)
			DRA7XX_CORE_IOPAD(0x357c, 0x90104)
			DRA7XX_CORE_IOPAD(0x3578, 0x90104)
			DRA7XX_CORE_IOPAD(0x3574, 0x90104)
			DRA7XX_CORE_IOPAD(0x3570, 0x90104)
			DRA7XX_CORE_IOPAD(0x356c, 0x90104)
			DRA7XX_CORE_IOPAD(0x3568, 0x90104) /*d23*/

		>;
	};


	i2c3_pins_default: i2c3_pins_default {
		pinctrl-single,pins = <
			DRA7XX_CORE_IOPAD(0x34c0, 0x50008)
			DRA7XX_CORE_IOPAD(0x34c4, 0x50008)
		>;
	};

	i2c4_pins_default: i2c4_pins_default {
		pinctrl-single,pins = <
			DRA7XX_CORE_IOPAD(0x36b0, 0x5000a)
			DRA7XX_CORE_IOPAD(0x36ac, 0x5000a)
			DRA7XX_CORE_IOPAD(0x34d4, 0x6000E)/*tp int gpio2_27*/
		>;
	};

	tp_pin: pinmux_tp_pin {
		pinctrl-single,pins = <
			DRA7XX_CORE_IOPAD(0x34d4, 0x6000E)/*tp int gpio2_27*/
		>;
	};

	mcasp2_pins_default: mcasp2_pins_default {
		pinctrl-single,pins = <
			DRA7XX_CORE_IOPAD(0x3698, 0x50003)
			DRA7XX_CORE_IOPAD(0x36f4, 0x50000)
			DRA7XX_CORE_IOPAD(0x36f8, 0xd0000)
			DRA7XX_CORE_IOPAD(0x3704, 0x50000)
			DRA7XX_CORE_IOPAD(0x3708, 0x50000)
			DRA7XX_CORE_IOPAD(0x370c, 0xd0000)
			DRA7XX_CORE_IOPAD(0x3710, 0xd0000)
			DRA7XX_CORE_IOPAD(0x3694, 0x00009)/* ahclk_clkout2 */
		>;
	};

	mcasp3_pins_default: mcasp3_pins_default {
		pinctrl-single,pins = <
			DRA7XX_CORE_IOPAD(0x3728, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp3_fsx.mcasp3_fsx */
			DRA7XX_CORE_IOPAD(0x372c, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mcasp3_axr0.mcasp3_axr0 */
			DRA7XX_CORE_IOPAD(0x3730, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp3_axr1.mcasp3_axr1 */
		>;
	};

	mcasp3_pins_sleep: mcasp3_pins_sleep {
		pinctrl-single,pins = <
			DRA7XX_CORE_IOPAD(0x3728, PIN_INPUT | MUX_MODE15)
			DRA7XX_CORE_IOPAD(0x372c, PIN_INPUT | MUX_MODE15)
			DRA7XX_CORE_IOPAD(0x3730, PIN_INPUT | MUX_MODE15)
		>;
	};
	mcasp4_pins_default: mcasp4_pins_default {
		pinctrl-single,pins = <
			DRA7XX_CORE_IOPAD(0x3734, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp3_aclkx.mcasp3_aclkx */
			DRA7XX_CORE_IOPAD(0x3738, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp3_fsx.mcasp3_fsx */
			DRA7XX_CORE_IOPAD(0x373c, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mcasp3_axr0.mcasp3_axr0 */
			DRA7XX_CORE_IOPAD(0x3740, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp3_axr1.mcasp3_axr1 */
			DRA7XX_CORE_IOPAD(0x36a0, PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* xref_clk2.mcasp3_ahclkx */
		>;
	};

	mcasp4_pins_sleep: mcasp4_pins_sleep {
		pinctrl-single,pins = <
			DRA7XX_CORE_IOPAD(0x3734, PIN_INPUT | MUX_MODE15)
			DRA7XX_CORE_IOPAD(0x3738, PIN_INPUT | MUX_MODE15)
			DRA7XX_CORE_IOPAD(0x373c, PIN_INPUT | MUX_MODE15)
			DRA7XX_CORE_IOPAD(0x3740, PIN_INPUT | MUX_MODE15)
		>;
	};

	mcasp5_pins_default: mcasp5_pins_default {
		pinctrl-single,pins = <
			DRA7XX_CORE_IOPAD(0x3744, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp5_aclkx.mcasp5_aclkx*/
			DRA7XX_CORE_IOPAD(0x3748, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp5_fsx.mcasp5_fsx*/
			DRA7XX_CORE_IOPAD(0x374c, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mcasp5_axr0.mcasp5_axr0*/
			DRA7XX_CORE_IOPAD(0x3750, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp5_axr1.mcasp5_axr1*/
			DRA7XX_CORE_IOPAD(0x3694, PIN_OUTPUT_PULLDOWN | MUX_MODE4) /* xref_clk0.mcasp5_ahclkx*/
		>;
	};

	mcasp5_pins_sleep: mcasp5_pins_sleep {
		pinctrl-single,pins = <
			DRA7XX_CORE_IOPAD(0x3744, PIN_INPUT | MUX_MODE15)
			DRA7XX_CORE_IOPAD(0x3748, PIN_INPUT | MUX_MODE15)
			DRA7XX_CORE_IOPAD(0x374c, PIN_INPUT | MUX_MODE15)
			DRA7XX_CORE_IOPAD(0x3750, PIN_INPUT | MUX_MODE15)
			DRA7XX_CORE_IOPAD(0x3694, PIN_INPUT | MUX_MODE15)
		>;
	};

	mcasp6_pins_default: mcasp6_pins_default {
		pinctrl-single,pins = <
			DRA7XX_CORE_IOPAD(0x36dc, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mcasp1_axr10.mcasp6_aclkx*/
			DRA7XX_CORE_IOPAD(0x36e0, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mcasp1_axr11.mcasp6_fsx*/
			DRA7XX_CORE_IOPAD(0x36d4, PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mcasp1_axr8.mcasp6_axr0*/
			DRA7XX_CORE_IOPAD(0x36d8, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mcasp1_axr9.mcasp6_axr1*/
			DRA7XX_CORE_IOPAD(0x3698, PIN_OUTPUT_PULLDOWN | MUX_MODE4) /* xref_clk1.mcasp6_ahclkx*/
		>;
	};

	mcasp6_pins_sleep: mcasp6_pins_sleep {
		pinctrl-single,pins = <
			DRA7XX_CORE_IOPAD(0x36dc, PIN_INPUT | MUX_MODE15)
			DRA7XX_CORE_IOPAD(0x36e0, PIN_INPUT | MUX_MODE15)
			DRA7XX_CORE_IOPAD(0x36d4, PIN_INPUT | MUX_MODE15)
			DRA7XX_CORE_IOPAD(0x36d8, PIN_INPUT | MUX_MODE15)
			DRA7XX_CORE_IOPAD(0x3698, PIN_INPUT | MUX_MODE15)
		>;
	};

	mcspi1_pins_default: mcspi1_pins_default {
		pinctrl-single,pins = <
			DRA7XX_CORE_IOPAD(0x37a4, 0x50000)
			DRA7XX_CORE_IOPAD(0x37b0, 0x50000)
			DRA7XX_CORE_IOPAD(0x37ac, 0x50000)
			DRA7XX_CORE_IOPAD(0x37a8, 0x50000)
			DRA7XX_CORE_IOPAD(0x37b4, 0x6000e) /*gpio7_11 hi3599 flag*/
		>;
	};

	mcspi2_pins_default: mcspi2_pins_default {
		pinctrl-single,pins = <
			DRA7XX_CORE_IOPAD(0x37c0, 0x50000)
			DRA7XX_CORE_IOPAD(0x37c8, 0x50000)
			DRA7XX_CORE_IOPAD(0x37c4, 0x50000)
			DRA7XX_CORE_IOPAD(0x37cc, 0x50000)
		>;
	};

	uart1_pins_default: uart1_pins_default {
		pinctrl-single,pins = <
			DRA7XX_CORE_IOPAD(0x37e0, 0xd0000)
			/*DRA7XX_CORE_IOPAD(0x37ec, 0x20000)*/
		>;
	};

	uart4_pins_default: uart4_pins_default {
		pinctrl-single,pins = <
			DRA7XX_CORE_IOPAD(0x373c, 0x50004)
			DRA7XX_CORE_IOPAD(0x3740, 0x10004)
		>;
	};

	uart10_pins_default: uart10_pins_default {
		pinctrl-single,pins = <
			DRA7XX_CORE_IOPAD(0x379c, 0x50002) /*uart10 cts*/
			DRA7XX_CORE_IOPAD(0x37a0, 0x10002) /*uart10 rts*/
		>;
	};



	cpsw_pins_default: cpsw_pins_default {
		pinctrl-single,pins = <
			/* Slave at addr 0x0 */
			DRA7XX_CORE_IOPAD(0x3660, 0x50101) /*rgmii0_txd1 rmii0_rxd1*/
			DRA7XX_CORE_IOPAD(0x3664, 0x50101) /*rgmii0_txd0   rmii0_rxd0*/
			DRA7XX_CORE_IOPAD(0x367c, 0x10001) /*rgmii0_rxd0   rmii0_txd0*/
			DRA7XX_CORE_IOPAD(0x3678, 0x10001) /*rgmii0_rxd1   rmii0_txd1*/
			DRA7XX_CORE_IOPAD(0x365c, 0x50101) /*rgmii0_txd2   rmii0_rxer*/
			DRA7XX_CORE_IOPAD(0x3658, 0x50101) /*rgmii0_txd3   rmii0_crs*/
			DRA7XX_CORE_IOPAD(0x3674, 0x10001) /*rgmii0_rxd2   rmii0_txen*/

			/* Slave at addr 0x1 */
		>;
	};

	cpsw_pins_sleep: cpsw_pins_sleep {
		pinctrl-single,pins = <
			/* Slave 1 */
			DRA7XX_CORE_IOPAD(0x3660, PIN_INPUT | MUX_MODE15)
			DRA7XX_CORE_IOPAD(0x3664, PIN_INPUT | MUX_MODE15)
			DRA7XX_CORE_IOPAD(0x367c, PIN_INPUT | MUX_MODE15)
			DRA7XX_CORE_IOPAD(0x3678, PIN_INPUT | MUX_MODE15)
			DRA7XX_CORE_IOPAD(0x365c, PIN_INPUT | MUX_MODE15)
			DRA7XX_CORE_IOPAD(0x3658, PIN_INPUT | MUX_MODE15)
			DRA7XX_CORE_IOPAD(0x3674, PIN_INPUT | MUX_MODE15)

			/* Slave 2 */
		>;
	};

	davinci_mdio_pins_default: davinci_mdio_pins_default {
		pinctrl-single,pins = <
			/* MDIO */
			DRA7XX_CORE_IOPAD(0x363c, PIN_OUTPUT_PULLUP | MUX_MODE0)
			DRA7XX_CORE_IOPAD(0x3640, PIN_INPUT_PULLUP | MUX_MODE0)
		>;
	};

	davinci_mdio_pins_sleep: davinci_mdio_pins_sleep {
		pinctrl-single,pins = <
			DRA7XX_CORE_IOPAD(0x363c, PIN_INPUT | MUX_MODE15)
			DRA7XX_CORE_IOPAD(0x3640, PIN_INPUT | MUX_MODE15)
		>;
	};

	hdmi_pins: pinmux_hdmi_pins {
		pinctrl-single,pins = <
			DRA7XX_CORE_IOPAD(0x3808, PIN_INPUT | MUX_MODE1)	/* i2c2_sda.hdmi1_ddc_scl */
			DRA7XX_CORE_IOPAD(0x380c, PIN_INPUT | MUX_MODE1)	/* i2c2_scl.hdmi1_ddc_sda */
		>;
	};

	mmc4_pins_ds: pinmux_mmc4_pins_ds {
		pinctrl-single,pins = <
			DRA7XX_CORE_IOPAD(0x37e8, PIN_INPUT_PULLUP | MUX_MODE3)
			DRA7XX_CORE_IOPAD(0x37ec, PIN_INPUT_PULLUP | MUX_MODE3)
			DRA7XX_CORE_IOPAD(0x37f0, PIN_INPUT_PULLUP | MUX_MODE3)
			DRA7XX_CORE_IOPAD(0x37f4, PIN_INPUT_PULLUP | MUX_MODE3)
			DRA7XX_CORE_IOPAD(0x37f8, PIN_INPUT_PULLUP | MUX_MODE3)
			DRA7XX_CORE_IOPAD(0x37fc, PIN_INPUT_PULLUP | MUX_MODE3)
		>;
	};

	mmc4_pins_default: mmc4_pins_default {
		pinctrl-single,pins = <
			DRA7XX_CORE_IOPAD(0x37e8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart1_ctsn.mmc4_clk */
			DRA7XX_CORE_IOPAD(0x37ec, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart1_rtsn.mmc4_cmd */
			DRA7XX_CORE_IOPAD(0x37f0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_rxd.mmc4_dat0 */
			DRA7XX_CORE_IOPAD(0x37f4, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_txd.mmc4_dat1 */
			DRA7XX_CORE_IOPAD(0x37f8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_ctsn.mmc4_dat2 */
			DRA7XX_CORE_IOPAD(0x37fc, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_rtsn.mmc4_dat3 */
		>;
	};

	mmc4_pins_hs: mmc4_pins_hs {
		pinctrl-single,pins = <
			DRA7XX_CORE_IOPAD(0x37e8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart1_ctsn.mmc4_clk */
			DRA7XX_CORE_IOPAD(0x37ec, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart1_rtsn.mmc4_cmd */
			DRA7XX_CORE_IOPAD(0x37f0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_rxd.mmc4_dat0 */
			DRA7XX_CORE_IOPAD(0x37f4, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_txd.mmc4_dat1 */
			DRA7XX_CORE_IOPAD(0x37f8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_ctsn.mmc4_dat2 */
			DRA7XX_CORE_IOPAD(0x37fc, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_rtsn.mmc4_dat3 */
		>;
	};

	mmc4_pins_sdr12: mmc4_pins_sdr12 {
		pinctrl-single,pins = <
			DRA7XX_CORE_IOPAD(0x37e8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart1_ctsn.mmc4_clk */
			DRA7XX_CORE_IOPAD(0x37ec, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart1_rtsn.mmc4_cmd */
			DRA7XX_CORE_IOPAD(0x37f0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_rxd.mmc4_dat0 */
			DRA7XX_CORE_IOPAD(0x37f4, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_txd.mmc4_dat1 */
			DRA7XX_CORE_IOPAD(0x37f8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_ctsn.mmc4_dat2 */
			DRA7XX_CORE_IOPAD(0x37fc, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_rtsn.mmc4_dat3 */
		>;
	};

	mmc4_pins_sdr25: mmc4_pins_sdr25 {
		pinctrl-single,pins = <
			DRA7XX_CORE_IOPAD(0x37e8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart1_ctsn.mmc4_clk */
			DRA7XX_CORE_IOPAD(0x37ec, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart1_rtsn.mmc4_cmd */
			DRA7XX_CORE_IOPAD(0x37f0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_rxd.mmc4_dat0 */
			DRA7XX_CORE_IOPAD(0x37f4, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_txd.mmc4_dat1 */
			DRA7XX_CORE_IOPAD(0x37f8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_ctsn.mmc4_dat2 */
			DRA7XX_CORE_IOPAD(0x37fc, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_rtsn.mmc4_dat3 */
		>;
	};
};

&dra7_iodelay_core {
	mmc1_iodelay_ddr50_conf: mmc1_iodelay_ddr50_conf {
		pinctrl-pin-array = <
			0x618 A_DELAY_PS(0) G_DELAY_PS(0)		/* CFG_MMC1_CLK_IN */
			0x624 A_DELAY_PS(0) G_DELAY_PS(0)		/* CFG_MMC1_CMD_IN */
			0x630 A_DELAY_PS(495) G_DELAY_PS(0)	/* CFG_MMC1_DAT0_IN */
			0x63C A_DELAY_PS(116) G_DELAY_PS(0)	/* CFG_MMC1_DAT1_IN */
			0x648 A_DELAY_PS(117) G_DELAY_PS(0)	/* CFG_MMC1_DAT2_IN */
			0x654 A_DELAY_PS(32) G_DELAY_PS(0)	/* CFG_MMC1_DAT3_IN */
			0x620 A_DELAY_PS(1224) G_DELAY_PS(0)	/* CFG_MMC1_CLK_OUT */
			0x62C A_DELAY_PS(0) G_DELAY_PS(0)		/* CFG_MMC1_CMD_OUT */
			0x638 A_DELAY_PS(44) G_DELAY_PS(0)	/* CFG_MMC1_DAT0_OUT */
			0x644 A_DELAY_PS(64) G_DELAY_PS(0)	/* CFG_MMC1_DAT1_OUT */
			0x650 A_DELAY_PS(79) G_DELAY_PS(0)	/* CFG_MMC1_DAT2_OUT */
			0x65C A_DELAY_PS(87) G_DELAY_PS(0)	/* CFG_MMC1_DAT3_OUT */
			0x628 A_DELAY_PS(0) G_DELAY_PS(0)		/* CFG_MMC1_CMD_OEN */
			0x634 A_DELAY_PS(0) G_DELAY_PS(0)		/* CFG_MMC1_DAT0_OEN */
			0x640 A_DELAY_PS(0) G_DELAY_PS(0)		/* CFG_MMC1_DAT1_OEN */
			0x64C A_DELAY_PS(0) G_DELAY_PS(0)		/* CFG_MMC1_DAT2_OEN */
			0x658 A_DELAY_PS(0) G_DELAY_PS(0)		/* CFG_MMC1_DAT3_OEN */
		>;
	};

	mmc1_iodelay_sdr104_conf: mmc1_iodelay_sdr104_conf {
		pinctrl-pin-array = <
			0x620 A_DELAY_PS(520) G_DELAY_PS(320)	/* CFG_MMC1_CLK_OUT */
			0x62c A_DELAY_PS(0) G_DELAY_PS(0)		/* CFG_MMC1_CMD_OUT */
			0x638 A_DELAY_PS(40) G_DELAY_PS(0)	/* CFG_MMC1_DAT0_OUT */
			0x644 A_DELAY_PS(83) G_DELAY_PS(0)	/* CFG_MMC1_DAT1_OUT */
			0x650 A_DELAY_PS(98) G_DELAY_PS(0)	/* CFG_MMC1_DAT2_OUT */
			0x65c A_DELAY_PS(106) G_DELAY_PS(0)	/* CFG_MMC1_DAT3_OUT */
			0x628 A_DELAY_PS(51) G_DELAY_PS(0)	/* CFG_MMC1_CMD_OEN */
			0x634 A_DELAY_PS(0) G_DELAY_PS(0)		/* CFG_MMC1_DAT0_OEN */
			0x640 A_DELAY_PS(363) G_DELAY_PS(0)	/* CFG_MMC1_DAT1_OEN */
			0x64c A_DELAY_PS(199) G_DELAY_PS(0)	/* CFG_MMC1_DAT2_OEN */
			0x658 A_DELAY_PS(273) G_DELAY_PS(0)	/* CFG_MMC1_DAT3_OEN */
		>;
	};

	mmc2_iodelay_ddr_1_8v_conf: mmc2_iodelay_ddr_1_8v_conf {
		pinctrl-pin-array = <
			0x18c A_DELAY_PS(0) G_DELAY_PS(0)		/* CFG_GPMC_A19_IN */
			0x1a4 A_DELAY_PS(121) G_DELAY_PS(0)	/* CFG_GPMC_A20_IN */
			0x1b0 A_DELAY_PS(0) G_DELAY_PS(0)		/* CFG_GPMC_A21_IN */
			0x1bc A_DELAY_PS(20) G_DELAY_PS(0)	/* CFG_GPMC_A22_IN */
			0x1c8 A_DELAY_PS(108) G_DELAY_PS(0)	/* CFG_GPMC_A23_IN */
			0x1d4 A_DELAY_PS(31) G_DELAY_PS(0)	/* CFG_GPMC_A24_IN */
			0x1e0 A_DELAY_PS(0) G_DELAY_PS(0)		/* CFG_GPMC_A25_IN */
			0x1ec A_DELAY_PS(24) G_DELAY_PS(0)	/* CFG_GPMC_A26_IN */
			0x1f8 A_DELAY_PS(0) G_DELAY_PS(0)		/* CFG_GPMC_A27_IN */
			0x360 A_DELAY_PS(0) G_DELAY_PS(0)		/* CFG_GPMC_CS1_IN */
			0x194 A_DELAY_PS(152) G_DELAY_PS(0)	/* CFG_GPMC_A19_OUT */
			0x1ac A_DELAY_PS(206) G_DELAY_PS(0)	/* CFG_GPMC_A20_OUT */
			0x1b8 A_DELAY_PS(78) G_DELAY_PS(0)	/* CFG_GPMC_A21_OUT */
			0x1c4 A_DELAY_PS(2) G_DELAY_PS(0)		/* CFG_GPMC_A22_OUT */
			0x1d0 A_DELAY_PS(266) G_DELAY_PS(0)	/* CFG_GPMC_A23_OUT */
			0x1dc A_DELAY_PS(0) G_DELAY_PS(0)		/* CFG_GPMC_A24_OUT */
			0x1e8 A_DELAY_PS(0) G_DELAY_PS(0)		/* CFG_GPMC_A25_OUT */
			0x1f4 A_DELAY_PS(43) G_DELAY_PS(0)	/* CFG_GPMC_A26_OUT */
			0x200 A_DELAY_PS(0) G_DELAY_PS(0)		/* CFG_GPMC_A27_OUT */
			0x368 A_DELAY_PS(0) G_DELAY_PS(0)		/* CFG_GPMC_CS1_OUT */
			0x190 A_DELAY_PS(0) G_DELAY_PS(0)		/* CFG_GPMC_A19_OEN */
			0x1a8 A_DELAY_PS(0) G_DELAY_PS(0)		/* CFG_GPMC_A20_OEN */
			0x1b4 A_DELAY_PS(0) G_DELAY_PS(0)		/* CFG_GPMC_A21_OEN */
			0x1c0 A_DELAY_PS(0) G_DELAY_PS(0)		/* CFG_GPMC_A22_OEN */
			0x1d8 A_DELAY_PS(0) G_DELAY_PS(0)		/* CFG_GPMC_A24_OEN */
			0x1e4 A_DELAY_PS(0) G_DELAY_PS(0)		/* CFG_GPMC_A25_OEN */
			0x1f0 A_DELAY_PS(0) G_DELAY_PS(0)		/* CFG_GPMC_A26_OEN */
			0x1fc A_DELAY_PS(0) G_DELAY_PS(0)		/* CFG_GPMC_A27_OEN */
			0x364 A_DELAY_PS(0) G_DELAY_PS(0)		/* CFG_GPMC_CS1_OEN */
		>;
	};

	mmc3_iodelay_sdr50_rev20_conf: mmc3_iodelay_sdr50_rev20_conf {
		pinctrl-single,pins = <
			0x678 (A_DELAY_PS(1085) | G_DELAY_PS(21)) 	/* CFG_MMC3_CLK_IN */
			0x680 (A_DELAY_PS(1269) | G_DELAY_PS(0)) 	/* CFG_MMC3_CLK_OUT */
			0x684 (A_DELAY_PS(0) | G_DELAY_PS(0)) 	/* CFG_MMC3_CMD_IN */
			0x688 (A_DELAY_PS(128) | G_DELAY_PS(0)) 	/* CFG_MMC3_CMD_OEN */
			0x68C (A_DELAY_PS(98) | G_DELAY_PS(0)) 	/* CFG_MMC3_CMD_OUT */
			0x690 (A_DELAY_PS(0) | G_DELAY_PS(0)) 	/* CFG_MMC3_DAT0_IN */
			0x694 (A_DELAY_PS(362) | G_DELAY_PS(0)) 	/* CFG_MMC3_DAT0_OEN */
			0x698 (A_DELAY_PS(0) | G_DELAY_PS(0)) 	/* CFG_MMC3_DAT0_OUT */
			0x69C (A_DELAY_PS(7) | G_DELAY_PS(0)) 	/* CFG_MMC3_DAT1_IN */
			0x6A0 (A_DELAY_PS(333) | G_DELAY_PS(0)) 	/* CFG_MMC3_DAT1_OEN */
			0x6A4 (A_DELAY_PS(0) | G_DELAY_PS(0)) 	/* CFG_MMC3_DAT1_OUT */
			0x6A8 (A_DELAY_PS(0) | G_DELAY_PS(0)) 	/* CFG_MMC3_DAT2_IN */
			0x6AC (A_DELAY_PS(402) | G_DELAY_PS(0)) 	/* CFG_MMC3_DAT2_OEN */
			0x6B0 (A_DELAY_PS(0) | G_DELAY_PS(0)) 	/* CFG_MMC3_DAT2_OUT */
			0x6B4 (A_DELAY_PS(203) | G_DELAY_PS(0)) 	/* CFG_MMC3_DAT3_IN */
			0x6B8 (A_DELAY_PS(549) | G_DELAY_PS(0)) 	/* CFG_MMC3_DAT3_OEN */
			0x6BC (A_DELAY_PS(1) | G_DELAY_PS(0)) 	/* CFG_MMC3_DAT3_OUT */
		>;
	};

	mmc4_iodelay_ds_rev11_conf: mmc4_iodelay_ds_rev11_conf {
		pinctrl-pin-array = <
			0x840 A_DELAY_PS(0) G_DELAY_PS(0)		/* CFG_UART1_CTSN_IN */
			0x848 A_DELAY_PS(0) G_DELAY_PS(0)		/* CFG_UART1_CTSN_OUT */
			0x84c A_DELAY_PS(96) G_DELAY_PS(0)	/* CFG_UART1_RTSN_IN */
			0x850 A_DELAY_PS(0) G_DELAY_PS(0)		/* CFG_UART1_RTSN_OEN */
			0x854 A_DELAY_PS(0) G_DELAY_PS(0)		/* CFG_UART1_RTSN_OUT */
			0x870 A_DELAY_PS(582) G_DELAY_PS(0)	/* CFG_UART2_CTSN_IN */
			0x874 A_DELAY_PS(0) G_DELAY_PS(0)		/* CFG_UART2_CTSN_OEN */
			0x878 A_DELAY_PS(0) G_DELAY_PS(0)		/* CFG_UART2_CTSN_OUT */
			0x87c A_DELAY_PS(391) G_DELAY_PS(0)	/* CFG_UART2_RTSN_IN */
			0x880 A_DELAY_PS(0) G_DELAY_PS(0)		/* CFG_UART2_RTSN_OEN */
			0x884 A_DELAY_PS(0) G_DELAY_PS(0)		/* CFG_UART2_RTSN_OUT */
			0x888 A_DELAY_PS(561) G_DELAY_PS(0)	/* CFG_UART2_RXD_IN */
			0x88c A_DELAY_PS(0) G_DELAY_PS(0)		/* CFG_UART2_RXD_OEN */
			0x890 A_DELAY_PS(0) G_DELAY_PS(0)		/* CFG_UART2_RXD_OUT */
			0x894 A_DELAY_PS(588) G_DELAY_PS(0)	/* CFG_UART2_TXD_IN */
			0x898 A_DELAY_PS(0) G_DELAY_PS(0)		/* CFG_UART2_TXD_OEN */
			0x89c A_DELAY_PS(0) G_DELAY_PS(0)		/* CFG_UART2_TXD_OUT */
		>;
	};

	mmc4_iodelay_ds_rev20_conf: mmc4_iodelay_ds_rev20_conf {
		pinctrl-pin-array = <
			0x840 A_DELAY_PS(0) G_DELAY_PS(0)		/* CFG_UART1_CTSN_IN */
			0x848 A_DELAY_PS(0) G_DELAY_PS(0)		/* CFG_UART1_CTSN_OUT */
			0x84c A_DELAY_PS(307) G_DELAY_PS(0)	/* CFG_UART1_RTSN_IN */
			0x850 A_DELAY_PS(0) G_DELAY_PS(0)		/* CFG_UART1_RTSN_OEN */
			0x854 A_DELAY_PS(0) G_DELAY_PS(0)		/* CFG_UART1_RTSN_OUT */
			0x870 A_DELAY_PS(785) G_DELAY_PS(0)	/* CFG_UART2_CTSN_IN */
			0x874 A_DELAY_PS(0) G_DELAY_PS(0)		/* CFG_UART2_CTSN_OEN */
			0x878 A_DELAY_PS(0) G_DELAY_PS(0)		/* CFG_UART2_CTSN_OUT */
			0x87c A_DELAY_PS(613) G_DELAY_PS(0)	/* CFG_UART2_RTSN_IN */
			0x880 A_DELAY_PS(0) G_DELAY_PS(0)		/* CFG_UART2_RTSN_OEN */
			0x884 A_DELAY_PS(0) G_DELAY_PS(0)		/* CFG_UART2_RTSN_OUT */
			0x888 A_DELAY_PS(683) G_DELAY_PS(0)	/* CFG_UART2_RXD_IN */
			0x88c A_DELAY_PS(0) G_DELAY_PS(0)		/* CFG_UART2_RXD_OEN */
			0x890 A_DELAY_PS(0) G_DELAY_PS(0)		/* CFG_UART2_RXD_OUT */
			0x894 A_DELAY_PS(835) G_DELAY_PS(0)	/* CFG_UART2_TXD_IN */
			0x898 A_DELAY_PS(0) G_DELAY_PS(0)		/* CFG_UART2_TXD_OEN */
			0x89c A_DELAY_PS(0) G_DELAY_PS(0)		/* CFG_UART2_TXD_OUT */
		>;
	};

	mmc4_iodelay_sdr12_hs_sdr25_rev11_conf: mmc4_iodelay_sdr12_hs_sdr25_rev11_conf {
		pinctrl-pin-array = <
			0x840 A_DELAY_PS(0) G_DELAY_PS(0)		/* CFG_UART1_CTSN_IN */
			0x848 A_DELAY_PS(2651) G_DELAY_PS(0)	/* CFG_UART1_CTSN_OUT */
			0x84c A_DELAY_PS(1572) G_DELAY_PS(0)	/* CFG_UART1_RTSN_IN */
			0x850 A_DELAY_PS(0) G_DELAY_PS(0)		/* CFG_UART1_RTSN_OEN */
			0x854 A_DELAY_PS(0) G_DELAY_PS(0)		/* CFG_UART1_RTSN_OUT */
			0x870 A_DELAY_PS(1913) G_DELAY_PS(0)	/* CFG_UART2_CTSN_IN */
			0x874 A_DELAY_PS(0) G_DELAY_PS(0)		/* CFG_UART2_CTSN_OEN */
			0x878 A_DELAY_PS(0) G_DELAY_PS(0)		/* CFG_UART2_CTSN_OUT */
			0x87c A_DELAY_PS(1721) G_DELAY_PS(0)	/* CFG_UART2_RTSN_IN */
			0x880 A_DELAY_PS(0) G_DELAY_PS(0)		/* CFG_UART2_RTSN_OEN */
			0x884 A_DELAY_PS(0) G_DELAY_PS(0)		/* CFG_UART2_RTSN_OUT */
			0x888 A_DELAY_PS(1891) G_DELAY_PS(0)	/* CFG_UART2_RXD_IN */
			0x88c A_DELAY_PS(0) G_DELAY_PS(0)		/* CFG_UART2_RXD_OEN */
			0x890 A_DELAY_PS(0) G_DELAY_PS(0)		/* CFG_UART2_RXD_OUT */
			0x894 A_DELAY_PS(1919) G_DELAY_PS(0)	/* CFG_UART2_TXD_IN */
			0x898 A_DELAY_PS(0) G_DELAY_PS(0)		/* CFG_UART2_TXD_OEN */
			0x89c A_DELAY_PS(0) G_DELAY_PS(0)		/* CFG_UART2_TXD_OUT */
		>;
	};

	mmc4_iodelay_sdr12_hs_sdr25_rev20_conf: mmc4_iodelay_sdr12_hs_sdr25_rev20_conf {
		pinctrl-pin-array = <
			0x840 A_DELAY_PS(0) G_DELAY_PS(0)		/* CFG_UART1_CTSN_IN */
			0x848 A_DELAY_PS(1147) G_DELAY_PS(0)	/* CFG_UART1_CTSN_OUT */
			0x84c A_DELAY_PS(1834) G_DELAY_PS(0)	/* CFG_UART1_RTSN_IN */
			0x850 A_DELAY_PS(0) G_DELAY_PS(0)		/* CFG_UART1_RTSN_OEN */
			0x854 A_DELAY_PS(0) G_DELAY_PS(0)		/* CFG_UART1_RTSN_OUT */
			0x870 A_DELAY_PS(2165) G_DELAY_PS(0)	/* CFG_UART2_CTSN_IN */
			0x874 A_DELAY_PS(0) G_DELAY_PS(0)		/* CFG_UART2_CTSN_OEN */
			0x878 A_DELAY_PS(0) G_DELAY_PS(0)		/* CFG_UART2_CTSN_OUT */
			0x87c A_DELAY_PS(1929) G_DELAY_PS(64)	/* CFG_UART2_RTSN_IN */
			0x880 A_DELAY_PS(0) G_DELAY_PS(0)		/* CFG_UART2_RTSN_OEN */
			0x884 A_DELAY_PS(0) G_DELAY_PS(0)		/* CFG_UART2_RTSN_OUT */
			0x888 A_DELAY_PS(1935) G_DELAY_PS(128)	/* CFG_UART2_RXD_IN */
			0x88c A_DELAY_PS(0) G_DELAY_PS(0)		/* CFG_UART2_RXD_OEN */
			0x890 A_DELAY_PS(0) G_DELAY_PS(0)		/* CFG_UART2_RXD_OUT */
			0x894 A_DELAY_PS(2172) G_DELAY_PS(44)	/* CFG_UART2_TXD_IN */
			0x898 A_DELAY_PS(0) G_DELAY_PS(0)		/* CFG_UART2_TXD_OEN */
			0x89c A_DELAY_PS(0) G_DELAY_PS(0)		/* CFG_UART2_TXD_OUT */
		>;
	};
};

&mmc1 {
	pinctrl-names = "default", "hs";
	pinctrl-0 = <&mmc1_pins_default>;
	pinctrl-1 = <&mmc1_pins_hs>;
	/delete-property/ vmmc-supply;
	/delete-property/ vmmc_aux-supply;
	vmmc-supply = <&vsys_3v3>;
	cd-gpios = <&gpio6 27 0>; /* gpio 219 */
	wp-gpios = <&gpio6 28 0>; /* gpio 220 */
};

&mmc2 {
	//pinctrl-names = "default", "hs", "ddr_1_8v";
	pinctrl-names = "default", "hs";
	pinctrl-0 = <&mmc2_pins_default>;
	pinctrl-1 = <&mmc2_pins_hs>;
	//pinctrl-2 = <&mmc2_pins_ddr_1_8v &mmc2_iodelay_ddr_1_8v_conf>;
    /delete-property/ cd-gpios;
    /delete-property/ vmmc-supply;
    /delete-property/ vmmc_aux-supply;
    /delete-property/ mmc-ddr-1_8v;
    /delete-property/ no-1-8-v;
    vmmc-supply = <&vsys_3v3>;
    ti,non-removable;
	bus-width = <8>;
	max-frequency = <96000000>;
};

&mmc3 {
	//pinctrl-names = "default", "hs", "sdr12", "sdr25", "sdr50";
	pinctrl-names = "default", "hs";
	status = "okay";
	pinctrl-0 = <&mmc3_pins_ds>;
	pinctrl-1 = <&mmc3_pins_hs>;
	//pinctrl-2 = <&mmc3_pins_sdr12>;
	//pinctrl-3 = <&mmc3_pins_sdr25>;
	//pinctrl-4 = <&mmc3_pins_sdr50 &mmc3_iodelay_sdr50_rev20_conf>;
	/delete-property/ vmmc-supply;
	/delete-property/ vmmc_aux-supply;
	/delete-property/ mmc-ddr-1_8v;
	/delete-property/ no-1-8-v;
	/delete-property/ sd-uhs-sdr12;
	/delete-property/ sd-uhs-sdr25;
	/delete-property/ sd-uhs-sdr50;
	/delete-property/ ti,non-removable;
	//cd-gpios = <&gpio1 15 1>;
	vmmc-supply = <&emmcex_oe>;
	bus-width = <8>;
	max-frequency = <96000000>;
};

&mmc4 {
	pinctrl-names = "default";
	status = "okay";
	pinctrl-0 = <&mmc4_pins_ds>;
	vmmc-supply = <&vmmcwl_fixed>;
	ti,non-removable;
	ti,needs-special-hs-handling;
	cap-power-off-card;
	keep-power-in-suspend;

	#address-cells = <1>;
	#size-cells = <0>;
	wlcore: wlcore@0 {
		compatible = "ti,wl1807";
		reg = <2>;
		interrupt-parent = <&gpio5>;
		interrupts = <17 IRQ_TYPE_LEVEL_HIGH>;
	};
};

/*&mmc4 {
	status = "okay";
	vmmc-supply = <&vmmcwl_fixed>;
	bus-width = <4>;
	cap-power-off-card;
	keep-power-in-suspend;
	ti,non-removable;
	max-frequency = <400000>;

	pinctrl-names = "default-rev11", "default", "hs-rev11", "hs", "sdr12-rev11", "sdr12", "sdr25-rev11", "sdr25";
	//pinctrl-names = "default";
	pinctrl-0 = <&mmc4_pins_default &mmc4_iodelay_ds_rev11_conf>;
	pinctrl-1 = <&mmc4_pins_default &mmc4_iodelay_ds_rev20_conf>;
	pinctrl-2 = <&mmc4_pins_hs &mmc4_iodelay_sdr12_hs_sdr25_rev11_conf>;
	pinctrl-3 = <&mmc4_pins_hs &mmc4_iodelay_sdr12_hs_sdr25_rev20_conf>;
	pinctrl-4 = <&mmc4_pins_sdr12 &mmc4_iodelay_sdr12_hs_sdr25_rev11_conf>;
	pinctrl-5 = <&mmc4_pins_sdr12 &mmc4_iodelay_sdr12_hs_sdr25_rev20_conf>;
	pinctrl-6 = <&mmc4_pins_sdr25 &mmc4_iodelay_sdr12_hs_sdr25_rev11_conf>;
	pinctrl-7 = <&mmc4_pins_sdr25 &mmc4_iodelay_sdr12_hs_sdr25_rev20_conf>;

	#address-cells = <1>;
	#size-cells = <0>;
	wlcore: wlcore@2 {
		compatible = "ti,wl1807";
		reg = <2>;
		interrupt-parent = <&gpio5>;
		interrupts = <17 IRQ_TYPE_LEVEL_HIGH>;
	};
};*/

&usb2_phy1 {
	phy-supply = <&vsys_3v3>;
};

&usb2_phy2 {
	phy-supply = <&vsys_3v3>;
};

&usb1 {
	//dr_mode = "otg";
	dr_mode = "host";
};

&usb2 {
	dr_mode = "host";
};

&omap_dwc3_1 {
	extcon = <&extcon_usb1>;
};

&omap_dwc3_2 {
	extcon = <&extcon_usb2>;
};

&cpu0 {
	vdd-supply = <&lp8733_buck0_reg>;
};

&ov2659_1 {
	remote-endpoint = <&vin1b>;
};

&vin1b {
	status = "okay";

	endpoint@2 {
		slave-mode;
		remote-endpoint = <&ov2659_1>;
	};
};

&vip1 {
	status = "okay";
};

&mailbox5 {
	status = "okay";
	mbox_ipu1_ipc3x: mbox_ipu1_ipc3x {
		status = "okay";
	};
	mbox_dsp1_ipc3x: mbox_dsp1_ipc3x {
		status = "okay";
	};
};

&mailbox6 {
	status = "okay";
	mbox_ipu2_ipc3x: mbox_ipu2_ipc3x {
		status = "okay";
	};
};

&mmu0_dsp1 {
	status = "okay";
};

&mmu1_dsp1 {
	status = "okay";
};

&mmu_ipu1 {
	status = "okay";
};

&mmu_ipu2 {
	status = "okay";
};

&ipu2 {
	//status = "disable";
	status = "okay";
	memory-region = <&ipu2_cma_pool>;
	mboxes = <&mailbox6 &mbox_ipu2_ipc3x>;
	timers = <&timer3>;
	watchdog-timers = <&timer4>, <&timer9>;
};

&ipu1 {
	status = "okay";
	memory-region = <&ipu1_cma_pool>;
	mboxes = <&mailbox5 &mbox_ipu1_ipc3x>;
	timers = <&timer11>;
	watchdog-timers = <&timer7>, <&timer8>;
};

&dsp1 {
	status = "okay";
	memory-region = <&dsp1_cma_pool>;
	mboxes = <&mailbox5 &mbox_dsp1_ipc3x>;
	timers = <&timer5>;
	watchdog-timers = <&timer10>;
};

&dss {
	pinctrl-names = "default";
	//pinctrl-0 = <&vout2_ds>;
	pinctrl-0 = <&vout3_ds>;
};

&pruss1_mdio {
	reset-gpios = <&gpio5 8 GPIO_ACTIVE_LOW>;
	reset-delay-us = <2>;   /* PHY datasheet states 1uS min */
	pruss1_eth0_phy: ethernet-phy@0 {
		reg = <0>;
		interrupt-parent = <&gpio3>;
		interrupts = <28 IRQ_TYPE_EDGE_FALLING>;
	};

	pruss1_eth1_phy: ethernet-phy@1 {
		reg = <1>;
		interrupt-parent = <&gpio3>;
		interrupts = <29 IRQ_TYPE_EDGE_FALLING>;
	};
};

&pruss2_mdio {
	status = "disabled";
	reset-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
	reset-delay-us = <2>;   /* PHY datasheet states 1uS min */
};

&epwmss1 {
	status = "okay";
};

&ehrpwm1 {
	status = "okay";
};

&dss {
	vdda_video-supply = <&vsys_3v3>;//fixed later pmic
	ports {
        /delete-node/ port@0;
		port@2 {
			reg = <2>;

			dpi_out: endpoint {
				remote-endpoint = <&lcd_in>;
				data-lines = <24>;
			};
		};
    };
};

&hdmi {
	vdda-supply = <&vsys_1v8>;//fixed later pmic
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&hdmi_pins>;

	port {
		hdmi_out: endpoint {
			remote-endpoint = <&hdmi_connector_in>;
		};
	};
};

&hdmi0 {
    status = "disabled";
	pinctrl-names = "default";
	//pinctrl-0 = <&hdmi_conn_pins>;
	//hpd-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;
		port {
			hdmi_connector_in: endpoint {
				remote-endpoint = <&hdmi_out>;
			};
		};
};
&cal {
	status = "okay";
};

/*
&csi2_0 {
	csi2_phy0: endpoint@0 {
		slave-mode;
		remote-endpoint = <&csi2_cam0>;
	};
};
*/

&dcan1 {
	status = "disabled";
};

&dss {
       ti,no-reset-on-init;
       ti,no-idle-on-init;
       ti,no-idle;
       dispc@58001000 {
               ti,no-reset-on-init;
               ti,no-idle-on-init;
               ti,no-idle;
       };
};

&gpio6 {
       ti,no-reset-on-init;
};

    Regards.

    June

  • 0 in reply to jian35385
    Prodigy 150 points

    Jian,

    I just modified the .dts file, and tested again.

    Normal execution of memtester.

    But there are many warning messages, each interval is 215 seconds.

    ipu2_cma@95000000 {
	compatible = "shared-dma-pool";
	reg = <0x0 0x95000000 0x0 0x4000000>;
	reusable;
	status = "okay";
	linux,phandle = <0xbd>;
	phandle = <0xbd>;
};

    am570x-mid.dts file

    Fullscreen 1781.am570x-mid.dts.txt Download 
    /*
 * Copyright (C) 2015-2016 Texas Instruments Incorporated - http://www.ti.com/
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */
/dts-v1/;

#include "dra72x.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/clk/ti-dra7-atl.h>
#include "am57xx-idk-common.dtsi"

/ {
	model = "TI AM5718 IDK";
	compatible = "ti,am5718-idk", "ti,am5718", "ti,dra7";

	chosen {
		 bootargs = "console=ttyO2,115200n8 root=/dev/mmcblk0p2 rw rootfstype=ext4 rootwait lpj=61475";
		 //bootargs = "console=ttyO2,115200n8 root=/dev/mmcblk1p2 rw rootfstype=ext4 rootwait";
	};
	aliases {
		ethernet4 = &pruss1_emac0;
		ethernet5 = &pruss1_emac1;
        /delete-property/ rtc1;
        rtc0 = &rv3028; 
                //sound0 = &sound0;
                sound1 = &hdmi;
		/delete-property/ ethernet2;
		/delete-property/ ethernet3;
		/delete-property/ ethernet4;
		/delete-property/ ethernet5;
		display0 = &lcd;
		display1 = &hdmi0;
	};

    /delete-node/ pruss1_eth;
    /delete-node/ pruss2_eth;
    /delete-node/ leds-iio;
    /delete-node/ encoder@0;

    lcd_bl: backlight {
        compatible = "pwm-backlight";
        pwms = <&ehrpwm1 0 50000 0>;
        //pwms = <&ecap0 0 50000 1>;
        brightness-levels = <1 25 50 75 128 158 175 200 220 254>;
        default-brightness-level = <4>;
        //enable-gpios = <&gpio5 6 GPIO_ACTIVE_HIGH>;
    };

    lcd: display {
         compatible = "panel-dpi";

         label = "lcd";

         enable-gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>;

         backlight = <&lcd_bl>;

         /*panel-timing {
             clock-frequency = <51000000>;
             hactive = <1024>;
             vactive = <600>;
             hfront-porch = <290>;
             hback-porch = <20>;
             hsync-len = <10>;
             vback-porch = <20>;
             vfront-porch = <10>;
             vsync-len = <5>;
             hsync-active = <0>;
             vsync-active = <0>;
             de-active = <1>;
             pixelclk-active = <0>;
         };*/
	panel-timing {
		clock-frequency = <65000000>;
		hactive = <1280>;
		vactive = <800>;
		hfront-porch = <24>;
		hback-porch = <24>;
		hsync-len = <2>;
		vfront-porch = <5>;
		vback-porch = <5>;
		vsync-len = <2>;
		hsync-active = <0>;
		vsync-active = <0>;
		de-active = <1>;
		pixelclk-active = <0>;
	};

         port {
            lcd_in: endpoint {
            remote-endpoint = <&dpi_out>;
            };
         };
     };

	memory@80000000 {
		device_type = "memory";
		reg = <0x0 0x80000000 0x0 0x40000000>;
	};

    ocp{
        /delete-node/ sata@4a141100;
        /delete-node/ rtc@48838000;
        /delete-node/ omap_dwc3_3@48900000;
    };

	evm_12v0: fixedregulator-evm12v0 {
		/* main supply */
		compatible = "regulator-fixed";
		regulator-name = "evm_12v0";
		regulator-min-microvolt = <12000000>;
		regulator-max-microvolt = <12000000>;
		regulator-always-on;
		regulator-boot-on;
		/*gpio = <&gpio6 13 0>;
		enable-active-high;*/
	};

	evm_5v0: fixedregulator-evm5v0 {
		/* Output 1 of TPS43351QDAPRQ1 on dra72-evm */
		/* Output 1 of LM5140QRWGTQ1 on dra71-evm */
		compatible = "regulator-fixed";
		regulator-name = "evm_5v0";
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
		vin-supply = <&evm_12v0>;
		regulator-always-on;
		regulator-boot-on;
	};

	vsys_3v3: fixedregulator-vsys3v3 {
		/* Output 2 of TPS43351QDAPRQ1 on dra72-evm */
		/* Output 2 of LM5140QRWGTQ1 on dra71-evm */
		compatible = "regulator-fixed";
		regulator-name = "vsys_3v3";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		vin-supply = <&evm_12v0>;
		regulator-always-on;
		regulator-boot-on;
	};

	emmcex_3v3: fixedregulator-emmcex3v3 {
		compatible = "regulator-fixed";
		regulator-name = "emmcex_3v3";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		vin-supply = <&evm_12v0>;
		gpio = <&gpio4 5 0>;
		startup-delay-us = <2000>;
		enable-active-high;
	};

	emmcex_oe: fixedregulator-emmcexoe {
		compatible = "regulator-fixed";
		regulator-name = "emmcex_oe";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		vin-supply = <&emmcex_3v3>;
		gpio = <&gpio1 14 0>;
		startup-delay-us = <2000>;
		enable-active-low;
	};

	vsys_1v8: fixedregulator-vsys1v8 {
		/* Output 2 of TPS43351QDAPRQ1 on dra72-evm */
		/* Output 2 of LM5140QRWGTQ1 on dra71-evm */
		compatible = "regulator-fixed";
		regulator-name = "vsys_1v8";
		regulator-min-microvolt = <1800000>;
		regulator-max-microvolt = <1800000>;
		vin-supply = <&evm_12v0>;
		regulator-always-on;
		regulator-boot-on;
	};


	vmmcwl_fixed: fixedregulator-mmcwl {
		compatible = "regulator-fixed";
		regulator-name = "vmmcwl_fixed";
		regulator-min-microvolt = <1800000>;
		regulator-max-microvolt = <1800000>;
		gpio = <&gpio4 7 0>;
		startup-delay-us = <70000>;
		enable-active-high;
		vin-supply = <&evm_12v0>;
		//regulator-always-on;
		//regulator-boot-on;
	};


    extcon_usb1: extcon_usb1 {
        compatible = "linux,extcon-usb-gpio";
        //id-gpio = <&gpio2 24 GPIO_ACTIVE_HIGH>;
        vbus-gpio = <&gpio6 12 GPIO_ACTIVE_HIGH>;
     };

    extcon_usb2: extcon_usb2 {
        compatible = "linux,extcon-usb-gpio";
        id-gpio = <&gpio2 25 GPIO_ACTIVE_HIGH>;
        //vbus-gpio = <&gpio6 13 GPIO_ACTIVE_HIGH>;
     };

	reserved-memory {
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

        cmem_block_mem_0: cmem_block_mem@a0000000 {
          reg = <0x0 0xa0000000 0x0 0x0c000000>;
          no-map;
          status = "okay";
        };

		ipu2_cma_pool: ipu2_cma@95000000 {
			compatible = "shared-dma-pool";
			reg = <0x0 0x95000000 0x0 0x4000000>;
			reusable;
			status = "okay";
		};

		dsp1_cma_pool: dsp1_cma@99000000 {
			compatible = "shared-dma-pool";
			reg = <0x0 0x99000000 0x0 0x4000000>;
			reusable;
			status = "okay";
		};

		ipu1_cma_pool: ipu1_cma@9d000000 {
			compatible = "shared-dma-pool";
			reg = <0x0 0x9d000000 0x0 0x2000000>;
			reusable;
			status = "okay";
		};
	};

    cmem {
        compatible = "ti,cmem";
        #address-cells = <1>;
        #size-cells = <0>;

        #pool-size-cells = <2>;

        status = "okay";

        cmem_block_0: cmem_block@0 {
            reg = <0>;
            memory-region = <&cmem_block_mem_0>;
            cmem-buf-pools = <1 0x0 0x0c000000>;
        };
    };
    gpio-keys {
        compatible = "gpio-keys";
        autorepeat;

		set {
			label = "Key_set";
			linux,code = <103>;
			gpios = <&gpio4 3 GPIO_ACTIVE_LOW>;
		};

		ok {
			label = "Key_ok";
			linux,code = <104>;
			gpios = <&gpio4 4 GPIO_ACTIVE_LOW>;
		};
		emmc {
			label = "Key_emmc";
			linux,code = <105>;
			gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
		};
    };
	leds {
		compatible = "gpio-leds";
		/*wdt-led {
			label = "wdt";
			gpios = <&gpio6 11 GPIO_ACTIVE_LOW>;
			default-state = "on";
			linux,default-trigger = "heartbeat";
		};*/


		h41-led {
			label = "h41";
			gpios = <&gpio4 8 GPIO_ACTIVE_HIGH>;
			default-state = "off";
			linux,default-trigger = "none";
		};

		h42-led {
			label = "h42";
			gpios = <&gpio4 9 GPIO_ACTIVE_HIGH>;
			default-state = "off";
			linux,default-trigger = "none";
		};

		h43-led {
			label = "h43";
			gpios = <&gpio4 11 GPIO_ACTIVE_HIGH>;
			default-state = "off";
			linux,default-trigger = "none";
		};

		h44-led {
			label = "h44";
			gpios = <&gpio4 12 GPIO_ACTIVE_HIGH>;
			default-state = "off";
			linux,default-trigger = "none";
		};

		h51-led {
			label = "h51";
			gpios = <&gpio5 4 GPIO_ACTIVE_HIGH>;
			default-state = "on";
			linux,default-trigger = "none";
		};

		h52-led {
			label = "h52";
			gpios = <&gpio6 7 GPIO_ACTIVE_HIGH>;
			default-state = "on";
			linux,default-trigger = "heartbeat";
		};

		h53-led {
			label = "h53";
			gpios = <&gpio6 14 GPIO_ACTIVE_HIGH>;
			default-state = "off";
			linux,default-trigger = "mmc2";
		};

		h54-led {
			label = "h54";
			gpios = <&gpio6 15 GPIO_ACTIVE_HIGH>;
			default-state = "off";
			linux,default-trigger = "none";
		};

		h61-led {
			label = "h61";
			gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>;
			default-state = "off";
			linux,default-trigger = "none";
		};

		h62-led {
			label = "h62";
			gpios = <&gpio3 29 GPIO_ACTIVE_HIGH>;
			default-state = "off";
			linux,default-trigger = "none";
		};

		h63-led {
			label = "h63";
			gpios = <&gpio7 23 GPIO_ACTIVE_HIGH>;
			default-state = "off";
			linux,default-trigger = "none";
		};

		h64-led {
			label = "h64";
			gpios = <&gpio7 31 GPIO_ACTIVE_HIGH>;
			default-state = "off";
			linux,default-trigger = "none";
		};
	};

	/* Dual mac ethernet application node on icss2 */
	pruss1_eth: pruss1_eth {
		status = "okay";
		compatible = "ti,am57-prueth";
		pruss = <&pruss1>;
		sram = <&ocmcram1>;
		interrupt-parent = <&pruss1_intc>;

		pruss1_emac0: ethernet-mii0 {
			phy-handle = <&pruss1_eth0_phy>;
			phy-mode = "mii";
			interrupts = <20>, <22>;
			interrupt-names = "rx", "tx";
			/* Filled in by bootloader */
			local-mac-address = [00 00 00 00 00 00];
		};

		pruss1_emac1: ethernet-mii1 {
			phy-handle = <&pruss1_eth1_phy>;
			phy-mode = "mii";
			interrupts = <21>, <23>;
			interrupt-names = "rx", "tx";
			/* Filled in by bootloader */
			local-mac-address = [00 00 00 00 00 00];
		};
	};
	sound0: sound@0 {
		compatible = "simple-audio-card";
		simple-audio-card,name = "DRA7xx-EVM";
		simple-audio-card,format = "i2s";
		//simple-audio-card,mclk-fs = <128>;
		simple-audio-card,bitclock-master = <&sound_master>;
		simple-audio-card,frame-master = <&sound_master>;
		simple-audio-card,widgets =
			"Headphone", "Headphone Jack",
			"Line", "Line In";
		simple-audio-card,routing =
			"Headphone Jack",	"SPK_LP",
			"Headphone Jack",	"SPK_RP",
			"LINPUT1",		"Line In",
			"RINPUT1",		"Line In";

		dailink0_master: simple-audio-card,cpu {
			sound-dai = <&mcasp4>;
		};

		sound_master: simple-audio-card,codec {
			sound-dai = <&tlv320aic34_a>;
			system-clock-frequency = <12000000>;
		};
	};
};


&cpu0_opp_table {
       opp_500@500000000 {
               opp-hz = /bits/ 64 <500000000>;
               opp-microvolt = <1060000 850000 1150000>,
                       <1060000 850000 1150000>;
               opp-supported-hw = <0xFF 0x01>;
       };
       opp_200@200000000 {
               opp-hz = /bits/ 64 <200000000>;
               opp-microvolt = <1060000 850000 1150000>,
                       <1060000 850000 1150000>;
               opp-supported-hw = <0xFF 0x01>;
       };

        /delete-node/ opp_od@1176000000;
        /delete-node/ opp_high@1500000000;
      
};

&mac {
	status = "okay";
	//dual_emac;
};

&phy_sel {
	rmii-clock-ext;
};

&cpsw_emac0 {
	phy_id = <&davinci_mdio>, <3>;
};

&cpsw_emac1 {
	phy_id = <&davinci_mdio>, <0>;
};

&davinci_mdio {
	pinctrl-names = "default", "sleep";
	pinctrl-0 = <&davinci_mdio_pins_default>;
	pinctrl-1 = <&davinci_mdio_pins_sleep>;
};

&i2c1 {
	status = "okay";

	lp8733: lp8733@60 {
		compatible = "ti,lp8733";
		reg = <0x60>;

		buck0-in-supply =<&vsys_3v3>;
		buck1-in-supply =<&vsys_3v3>;
		ldo0-in-supply =<&evm_5v0>;
		ldo1-in-supply =<&evm_5v0>;

		lp8733_regulators: regulators {
			lp8733_buck0_reg: buck0 {
				/* FB_B0 -> LP8733-BUCK1 - VPO_S1_AVS - VDD_CORE_AVS (core, mpu, gpu) */
				regulator-name = "lp8733-buck0";
				regulator-min-microvolt = <850000>;
				regulator-max-microvolt = <1250000>;
				regulator-always-on;
				regulator-boot-on;
			};

			lp8733_buck1_reg: buck1 {
				/* FB_B1 -> LP8733-BUCK2 - VPO_S2_AVS - VDD_DSP_AVS (DSP/eve/iva) */
				regulator-name = "lp8733-buck1";
				regulator-min-microvolt = <850000>;
				regulator-max-microvolt = <1250000>;
				regulator-boot-on;
				regulator-always-on;
			};

			lp8733_ldo0_reg: ldo0 {
				/* LDO0 -> LP8733-LDO1 - VPO_L1_3V3 - VDDSHV8 (optional) */
				regulator-name = "lp8733-ldo0";
				regulator-min-microvolt = <3300000>;
				regulator-max-microvolt = <3300000>;
				regulator-boot-on;
				regulator-always-on;
			};

			lp8733_ldo1_reg: ldo1 {
				/* LDO1 -> LP8733-LDO2 - VPO_L2_3V3 - VDDA_USB3V3 */
				regulator-name = "lp8733-ldo1";
				regulator-min-microvolt = <3300000>;
				regulator-max-microvolt = <3300000>;
				regulator-always-on;
				regulator-boot-on;
			};
		};
	};

	lp8732: lp8732@61 {
		compatible = "ti,lp8732";
		reg = <0x61>;

		buck0-in-supply =<&vsys_3v3>;
		buck1-in-supply =<&vsys_3v3>;
		ldo0-in-supply =<&vsys_3v3>;
		ldo1-in-supply =<&vsys_3v3>;

		lp8732_regulators: regulators {
			lp8732_buck0_reg: buck0 {
				/* FB_B0 -> LP8732-BUCK1 - VPO_S3_1V8 - VDDS_1V8 */
				regulator-name = "lp8732-buck0";
				regulator-min-microvolt = <1800000>;
				regulator-max-microvolt = <1800000>;
				regulator-always-on;
				regulator-boot-on;
			};

			lp8732_buck1_reg: buck1 {
				/* FB_B1 -> LP8732-BUCK2 - VPO_S4_DDR - VDD_DDR_1V35 */
				regulator-name = "lp8732-buck1";
				regulator-min-microvolt = <1350000>;
				regulator-max-microvolt = <1350000>;
				regulator-boot-on;
				regulator-always-on;
			};

			lp8732_ldo0_reg: ldo0 {
				/* LDO0 -> LP8732-LDO1 - VPO_L3_1V8 - VDA_1V8_PLL */
				regulator-name = "lp8732-ldo0";
				regulator-min-microvolt = <1800000>;
				regulator-max-microvolt = <1800000>;
				regulator-boot-on;
				regulator-always-on;
			};

			lp8732_ldo1_reg: ldo1 {
				/* LDO1 -> LP8732-LDO2 - VPO_L4_1V8 - VDA_1V8_PHY */
				regulator-name = "lp8732-ldo1";
				regulator-min-microvolt = <1800000>;
				regulator-max-microvolt = <1800000>;
				regulator-always-on;
				regulator-boot-on;
			};
		};
	};

    	rtc_pcf8563: rtc@51 {
            compatible = "nxp,pcf8563";
            reg = <0x51>;
	    status = "disable";
            interrupt-parent = <&gpio6>;
            interrupts = <16 IRQ_TYPE_EDGE_FALLING>;
        };

        /delete-node/ tc358778@0e;
        /delete-node/ tpic2810@60;
    	tps659038@58 {
           /delete-node/ tps659038_usb;
        };
	ov2659@30 {
	    status = "disabled";
	};
        PCM1862: PCM1860@4a {

        compatible = "ti,pcm18xx";
             reg = <0x4a>;
        };
        PCM1863: PCM1861@4b {
        compatible = "ti,pcm18xx";
            reg = <0x4b>;
        };
        is31fl3236: led-controller@3c {
	        compatible = "issi,is31fl3236";
	        reg = <0x3c>;
	        #address-cells = <1>;
	        #size-cells = <0>;

	        led@1 {
		       reg = <1>;
		       label = "AngelLed";
               linux,default-trigger = "default-off";
	        };
        };

        lkt4106: lkt4106@28 {
        compatible = "lkt4106";
             reg = <0x28>;
        };

        rv3028: rv3028@52 {
		compatible = "microcrystal,rv3028";
		reg = <0x52>;
		interrupt-parent = <&gpio1>;
		interrupts = <0 IRQ_TYPE_EDGE_FALLING>;
        };
};


&i2c3 {
	pinctrl-names = "default";
	pinctrl-0 = <&i2c3_pins_default>;

	clock-frequency = <400000>;
	status = "okay";
	wm8960: wm8960@1a {
		#sound-dai-cells = <0>;
        compatible = "wlf,wm8960";
        reg = <0x1a>;
        wlf,shared-lrclk;

       };
	eeprom_core: eeprom_core@50 {
        compatible = "atmel,24c256";
        reg = <0x50>;
        pagesize = <32>;
        status = "okay";
		     };

};

/*
&i2c4 {
	status = "okay";
	clock-frequency = <400000>;

	pinctrl-names = "default";
	pinctrl-0 = <&i2c4_pins_default>;

        PCM1860: PCM1860@4a {

        compatible = "ti,pcm18xx";
           reg = <0x4a>;
        };
        PCM1861: PCM1861@4b {
        compatible = "ti,pcm18xx";
        reg = <0x4b>;
        };
        AIC31: AIC31@1b {
         compatible = "ti,AIC31XX";
               reg = <0x1b>;
        };
        AIC31_2: AIC31@18 {
         compatible = "ti,AIC31XX";
               reg = <0x18>;
        };

};
*/
&i2c4 {
	status = "okay";
	clock-frequency = <400000>;

	pinctrl-names = "default";
	pinctrl-0 = <&i2c4_pins_default>;

	 tlv320aic34_a: tlv320aic34_a@1a {
                #sound-dai-cells = <0>;
                compatible = "ti,tlv320aic3x";
                reg = <0x1a>;
                adc-settle-ms = <40>;
                ai3x-micbias-vg = <1>;
                status = "disabled";

                AVDD-supply = <&vsys_3v3>;
                IOVDD-supply = <&vsys_3v3>;
                DRVDD-supply = <&vsys_3v3>;
		DVDD-supply = <&vsys_1v8>;
        };
	aic34_1@1a {
        compatible = "ti,aic3x";
        reg  = <0x1a>;
  
    };
    aic34_2@1b {
        compatible = "ti,aic3x";
        reg = <0x1b>;
    };
  
  
    mcp4441@2d {
	status = "disabled";
    	compatible = "microchip,mcp4441-103";
        reg = <0x2d>;
        gpio-addr-a0 = <&gpio2 29 GPIO_ACTIVE_LOW>;
    };

    ds1881_1@28 {
    	compatible = "maxim,ds1881-045";
        reg = <0x28>;
        enable-gpios = <&gpio2 29 GPIO_ACTIVE_LOW>;
    };

    /* PCM1860: PCM1860@4a {

        compatible = "ti,pcm18xx";
           reg = <0x4a>;
     };
        PCM1861: PCM1861@4b {
        compatible = "ti,pcm18xx";
        reg = <0x4b>;
        };
        AIC31: AIC31@1b {
         compatible = "ti,AIC31XX";
               reg = <0x1b>;
        };
        AIC31_2: AIC31@18 {
         compatible = "ti,AIC31XX";
               reg = <0x18>;
        };
     */
	/*hy461x@38 {
		compatible = "qcom,hy461x";
		reg = <0x38>;
		//pinctrl-names = "default";
		//pinctrl-0 = <&tp_pin>;

		qcom,ts-gpio-reset = <&gpio2 2 GPIO_ACTIVE_HIGH>;
		qcom,ts-gpio-irq = <&gpio2 27 GPIO_ACTIVE_HIGH>;

		qcom,max-x = <1024>;
		qcom,max-y = <600>;
		qcom,hard-reset-delay-ms = <220>;
		qcom,soft-reset-delay-ms = <220>;
	};

	goodix_ts@5d {
		compatible = "goodix,gt9xx";
		reg = <0x5d>;
		goodix,irq-gpio = <&gpio2 27 IRQ_TYPE_EDGE_RISING>;
		goodix,rst-gpio = <&gpio2 2 GPIO_ACTIVE_LOW>;
		goodix,cfg-group2 = [
00 00 05 20 03 05 0D 00 01 C8 28 0F 50 32 03 05 00 00 00 00 00 00 00 00 00 00 00 90 30 AA 20 1E 0C 08 00 00 00 9A 02 2D 00 00 00 00 00 00 00 00 00 00 00 0F 2D 94 C5 02 07 00 00 04 E0 10 00 B8 14 00 92 1A 00 7A 20 00 65 28 00 64 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 19 18 17 16 15 14 11 10 0F 0E 0D 0C 09 08 07 06 05 04 01 00 00 00 00 00 00 00 00 00 00 00 2A 29 28 27 26 25 24 23 22 21 20 1F 1E 1C 1B 19 14 13 12 11 10 0F 0E 0D 0C 0A 08 07 06 04 02 00 00 00 00 00 00 00 00 00 00 00 43 01
		];
	};

	tlv320aic3106: tlv320aic3106@1b {
		#sound-dai-cells = <0>;
		compatible = "ti,tlv320aic3106";
		reg = <0x1b>;
		adc-settle-ms = <40>;
		ai3x-micbias-vg = <1>;
		assigned-clocks = <&clkoutmux2_clk_mux>;
		assigned-clock-parents = <&sys_clk2_dclk_div>;
		status = "okay";
		gpio-reset = <&gpio5 14 GPIO_ACTIVE_HIGH>;

		AVDD-supply = <&vsys_3v3>;
		IOVDD-supply = <&vsys_3v3>;
		DRVDD-supply = <&vsys_3v3>;
		DVDD-supply = <&vsys_1v8>;
	};
	tlv320aic3106: tlv320aic3106@18 {
		#sound-dai-cells = <0>;
		compatible = "ti,tlv320aic3106";
		reg = <0x18>;
		adc-settle-ms = <40>;
		ai3x-micbias-vg = <1>;		
		assigned-clocks = <&clkoutmux2_clk_mux>;
		assigned-clock-parents = <&sys_clk2_dclk_div>;
		status = "okay";

		AVDD-supply = <&vsys_3v3>;
		IOVDD-supply = <&vsys_3v3>;
		DRVDD-supply = <&vsys_3v3>;
		DVDD-supply = <&vsys_1v8>;
	};
	gpio_csi2_adap: tca6416@20 {
		status = "okay";
		compatible = "ti,tca6416";
		reg = <0x20>;
		gpio-controller;
		#gpio-cells = <2>;
	};

	ov490@36 {
		compatible = "ovti,ov490";
		reg = <0x36>;

		mux-gpios = <&gpio_csi2_adap 0	GPIO_ACTIVE_LOW>,
			    <&gpio_csi2_adap 1	GPIO_ACTIVE_HIGH>,
			    <&gpio_csi2_adap 3	GPIO_ACTIVE_HIGH>,
			    <&gpio_csi2_adap 4	GPIO_ACTIVE_LOW>;
		port {
			csi2_cam0: endpoint@0 {
				clock-lanes = <0>;
				data-lanes = <1 2>;
				remote-endpoint = <&csi2_phy0>;
			};
		};
	};
*/

	tmp112: tmp112@48 {
		compatible = "ti,tmp102";
		reg = <0x48>;
	};
};

&mcspi1 {
	pinctrl-names = "default";
	pinctrl-0 = <&mcspi1_pins_default>;
	status = "okay";
	ti,pindir-d0-out-d1-in;
	ti,spi-num-cs = <1>;

/*
	spidev1: spi@0 {
		compatible = "rohm,dh2228fv";
		reg = <0>;
		spi-max-frequency = <500000>;
	};
*/
	 hi3599@0 {
		 compatible = "hi,hi3599";
		 reg = <0>;
		 interrupt-parent = <&gpio7>;
		 interrupts = <11 0>;
		 irq-gpio = <&gpio7 11 0>;
		 spi-max-frequency = <5000000>;
	 };
};

&mcspi2 {
	pinctrl-names = "default";
	pinctrl-0 = <&mcspi2_pins_default>;
	status = "okay";
	ti,pindir-d0-out-d1-in;
	ti,spi-num-cs = <1>;

/*
	spidev2: spi@0 {
		compatible = "rohm,dh2228fv";
		reg = <0>;
		spi-max-frequency = <500000>;
	};
*/
	 hi8429@0 {
		 compatible = "hi,hi8429";
		 reg = <0>;
		 interrupt-parent = <&gpio5>;
		 interrupts = <6 0>;
		 irq-gpio = <&gpio5 6 0>;
		 rst-gpio = <&gpio5 7 0>;
		 sel0-gpio = <&gpio5 9 0>;
		 sel1-gpio = <&gpio5 8 0>;
		 spi-max-frequency = <5000000>;
	 };
};

&uart1 {
    compatible = "ti,omap2-uart";
	pinctrl-names = "default";
    status = "disabled";
	pinctrl-0 = <&uart1_pins_default>;

    /* GPIO7 pin 25 for data direction */
    //rts-gpio = <&gpio7 25 GPIO_ACTIVE_HIGH>;
    //rs485-rts-active-high;
    //rs485-rts-delay = <1 1>;      /* in milliseconds */
    //linux,rs485-enabled-at-boot-time;
};

&uart6 {
     pinctrl-names = "default";
     status = "disabled";
};
&uart10 {
	pinctrl-names = "default";
	pinctrl-0 = <&uart10_pins_default>;

	status = "disabled";
};



&mcspi3 {
	status = "disabled";
};

&atl {
	assigned-clocks = <&abe_dpll_sys_clk_mux>,
			  <&atl_gfclk_mux>,
			  <&dpll_abe_ck>,
			  <&dpll_abe_m2x2_ck>,
			  <&atl_clkin2_ck>;
	assigned-clock-parents = <&sys_clkin2>, <&dpll_abe_m2_ck>;
	//assigned-clock-rates = <0>, <0>, <180633600>, <361267200>, <5644800>;
	assigned-clock-rates = <0>, <0>, <180633600>, <361267200>, <11289600>;

	status = "okay";

	atl2 {
		bws = <DRA7_ATL_WS_MCASP2_FSX>;
		aws = <DRA7_ATL_WS_MCASP3_FSX>;
	};
};

&mcasp4 {
	#sound-dai-cells = <0>;

	assigned-clocks = <&mcasp4_ahclkx_mux>;
	assigned-clock-parents = <&atl_clkin2_ck>;

	pinctrl-names = "default", "sleep";
	pinctrl-0 = <&mcasp4_pins_default>;
	pinctrl-1 = <&mcasp4_pins_sleep>;
	status = "disabled";

	op-mode = <0>;	/* MCASP_IIS_MODE */
	tdm-slots = <2>;
	/* 4 serializers */
	serial-dir = <	/* 0: INACTIVE, 1: TX, 2: RX */
		1 0 0 0
	>;
	tx-num-evt = <32>;
	rx-num-evt = <32>;
};

&mcasp2 {
	status = "disabled";
	#sound-dai-cells = <0>;

	assigned-clocks = <&mcasp2_ahclkx_mux>;
	assigned-clock-parents = <&sys_clkin2>;

	pinctrl-names = "default";
	pinctrl-0 = <&mcasp2_pins_default>;
	

	op-mode = <0>;	/* MCASP_IIS_MODE */
	tdm-slots = <2>;
	/* 4 serializers */
	serial-dir = <	/* 0: INACTIVE, 1: TX, 2: RX */
		1 2 0 0
		/*1 2 1 2*/
		/*0 0 1 2*/
	>;
	tx-num-evt = <32>;
	rx-num-evt = <32>;
};

&mcasp5 {
	status = "disable";
	#sound-dai-cells = <0>;
	pinctrl-names = "default", "sleep";
	pinctrl-0 = <&mcasp5_pins_default>;
	pinctrl-1 = <&mcasp5_pins_sleep>;

	op-mode = <0>;	/* MCASP_IIS_MODE */
	tdm-slots = <2>;
	/* 4 serializers */
	serial-dir = <	/* 0: INACTIVE, 1: TX, 2: RX */
		1 2 0 0
	>;
	tx-num-evt = <32>;
	rx-num-evt = <32>;
};

&mcasp6 {
	status = "disable";
	#sound-dai-cells = <0>;

	assigned-clocks = <&mcasp6_ahclkx_mux>;
	assigned-clock-parents = <&atl_clkin2_ck>;

	pinctrl-names = "default", "sleep";
	pinctrl-0 = <&mcasp6_pins_default>;
	pinctrl-1 = <&mcasp6_pins_sleep>;

	op-mode = <0>;	/* MCASP_IIS_MODE */
	tdm-slots = <2>;
	/* 4 serializers */
	serial-dir = <	/* 0: INACTIVE, 1: TX, 2: RX */
		1 2 0 0
	>;
	tx-num-evt = <32>;
	rx-num-evt = <32>;
};

&dra7_pmx_core {
	pinctrl-names = "default";
	pinctrl-0 = <&board_pins>;

	board_pins: pinmux_board_pins {
		pinctrl-single,pins = <

			DRA7XX_CORE_IOPAD(0x3724, 0x200e) /*gpio5_13 */
			DRA7XX_CORE_IOPAD(0x34c8, 0x6000e) /*gpio2_24 usb1 id*/  
			DRA7XX_CORE_IOPAD(0x34cc, 0x6000e) /*gpio2_25 usb2 id*/ 
			DRA7XX_CORE_IOPAD(0x3680, 0x90000)/* usb drv */
			DRA7XX_CORE_IOPAD(0x3680, 0xa000e)/* usb drv */
			DRA7XX_CORE_IOPAD(0x371c, 0x4000e) /*gpio2_29 hp det*/

			DRA7XX_CORE_IOPAD(0x37bc, 0x2000e)	/* gpio7_13 wifi wl-reg-on */ 
			DRA7XX_CORE_IOPAD(0x3728, 0x8000e) /* gpio5_14 spk sdn*/
			DRA7XX_CORE_IOPAD(0x3778, 0x20000) /* gpio6_11 camera pwdn*/

			DRA7XX_CORE_IOPAD(0x3774, 0x20000)/* gpio6_10 wdt_enable */
			DRA7XX_CORE_IOPAD(0x3778, 0x20000)/* gpio6_11 wdt_feed */
			DRA7XX_CORE_IOPAD(0x3714, 0x6000e)/* gpio1_4 power_down */
			DRA7XX_CORE_IOPAD(0x36c0, 0x6000e)/* gpio5_5 power_fault */
			DRA7XX_CORE_IOPAD(0x3720, 0x2000e)/* gpio1_5 pwr_4g */
			DRA7XX_CORE_IOPAD(0x3684, 0x8000e)/* gpio6_13 pwr_wifi pull_down*/
			DRA7XX_CORE_IOPAD(0x3580, 0x0000e)/* gpio4_7 wl_en */
			DRA7XX_CORE_IOPAD(0x3584, 0x0000e)/* gpio4_8 h4 */
			DRA7XX_CORE_IOPAD(0x3588, 0x0000e)/* gpio4_9 h4 */
			DRA7XX_CORE_IOPAD(0x3590, 0x0000e)/* gpio4_11 h4 */
			DRA7XX_CORE_IOPAD(0x3594, 0x0000e)/* gpio4_12 h4 */
			DRA7XX_CORE_IOPAD(0x36bc, 0x0000e)/* gpio5_4 h5 */
			DRA7XX_CORE_IOPAD(0x3718, 0x0000e)/* gpio6_7 h5 */
			DRA7XX_CORE_IOPAD(0x3688, 0x00000)/* gpio6_14 h5 */
			DRA7XX_CORE_IOPAD(0x368c, 0x00000)/* gpio6_15 h5 */
			DRA7XX_CORE_IOPAD(0x3470, 0x0000e)/* gpio2_2 h6 */
			DRA7XX_CORE_IOPAD(0x3558, 0x0000e)/* gpio3_29 h6 */
			DRA7XX_CORE_IOPAD(0x37e4, 0x0000e)/* gpio7_23 h6 */
			DRA7XX_CORE_IOPAD(0x36a4, 0x0000e)/* gpio7_31 h6 */
			DRA7XX_CORE_IOPAD(0x3560, 0x2000e)/* gpio3_31 sim_switch*/
			DRA7XX_CORE_IOPAD(0x3564, 0x0000e)/* gpio4_0 pwr_on_off*/
			DRA7XX_CORE_IOPAD(0x3568, 0x1000e)/* gpio4_1 rf_switch*/
			DRA7XX_CORE_IOPAD(0x356c, 0x1000e)/* gpio4_2 4g reset*/
			DRA7XX_CORE_IOPAD(0x3570, 0x6000e)/* gpio4_3 key s3*/
			DRA7XX_CORE_IOPAD(0x3574, 0x6000e)/* gpio4_4 key s2*/
			DRA7XX_CORE_IOPAD(0x37d0, 0x8000e)/* ext emmc enable dcan1_tx.gpio1_14 */
			DRA7XX_CORE_IOPAD(0x3578, 0x0000e)/* gpio4_5 ext emmc pwr pull down*/
			DRA7XX_CORE_IOPAD(0x3818, 0x6000e)/* gpio1_0 rtc int */
			DRA7XX_CORE_IOPAD(0x37d4, 0xe000e)/* gpio1_15 ext emmc key */
			DRA7XX_CORE_IOPAD(0x36c4, 0x5000e)/* gpio5_6 hi8429 int */
			DRA7XX_CORE_IOPAD(0x36c8, 0x1000e)/* gpio5_7 hi8429 rstn */
			DRA7XX_CORE_IOPAD(0x36cc, 0x1000e)/* gpio5_8 hi8429 sel0 */
			DRA7XX_CORE_IOPAD(0x36d0, 0x1000e)/* gpio5_9 hi8429 sel1 */
			DRA7XX_CORE_IOPAD(0x3644, 0x6000e) /*wl int gpio5_17*/
			DRA7XX_CORE_IOPAD(0x371c, 0xa000e) /* gpio2_29 a0 pin*/
			DRA7XX_CORE_IOPAD(0x3690, 0x10000) /* gpio6_16 */
			DRA7XX_CORE_IOPAD(0x369c, 0x1000e) /* gpio6_19 */
		>;
	};

	mmc1_pins_default: mmc1_pins_default {
		pinctrl-single,pins = <
			DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
			DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
			DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
			DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
			DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */
			DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */
			DRA7XX_CORE_IOPAD(0x376c, 0xd000e) /* mmc1_sdcd.gpio6_27 */
			DRA7XX_CORE_IOPAD(0x3770, 0xd000e) /* mmc1_sdwp.gpio6_28 */
		>;
	};

	mmc1_pins_hs: mmc1_pins_hs {
		pinctrl-single,pins = <
			DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
			DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
			DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
			DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
			DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */
			DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */
			DRA7XX_CORE_IOPAD(0x376c, 0xd000e) /* mmc1_sdcd.gpio6_27 */
			DRA7XX_CORE_IOPAD(0x3770, 0xd000e) /* mmc1_sdwp.gpio6_28 */
		>;
	};

	mmc2_pins_default: mmc2_pins_default {
		pinctrl-single,pins = <
			DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */
			DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
			DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
			DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
			DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
			DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
			DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
			DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
			DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
			DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
		>;
	};

	mmc2_pins_hs: mmc2_pins_hs {
		pinctrl-single,pins = <
			DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */
			DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
			DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
			DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
			DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
			DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
			DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
			DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
			DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
			DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
		>;
	};

	mmc2_pins_ddr_1_8v: mmc2_pins_ddr_1_8v {
		pinctrl-single,pins = <
			DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a23.mmc2_clk */
			DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
			DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
			DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
			DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
			DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
			DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
			DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
			DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
			DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
		>;
	};

	mmc3_pins_ds: pinmux_mmc3_pins_ds {
		pinctrl-single,pins = <
			DRA7XX_CORE_IOPAD(0x377c, PIN_INPUT_PULLUP | MUX_MODE0) 	/* mmc3_clk.mmc3_clk */
			DRA7XX_CORE_IOPAD(0x3780, PIN_INPUT_PULLUP | MUX_MODE0) 	/* mmc3_cmd.mmc3_cmd */
			DRA7XX_CORE_IOPAD(0x3784, PIN_INPUT_PULLUP | MUX_MODE0) 	/* mmc3_dat0.mmc3_dat0 */
			DRA7XX_CORE_IOPAD(0x3788, PIN_INPUT_PULLUP | MUX_MODE0) 	/* mmc3_dat1.mmc3_dat1 */
			DRA7XX_CORE_IOPAD(0x378c, PIN_INPUT_PULLUP | MUX_MODE0) 	/* mmc3_dat2.mmc3_dat2 */
			DRA7XX_CORE_IOPAD(0x3790, PIN_INPUT_PULLUP | MUX_MODE0) 	/* mmc3_dat3.mmc3_dat3 */
			DRA7XX_CORE_IOPAD(0x3794, PIN_INPUT_PULLUP | MUX_MODE0) 	/* mmc3_dat4.mmc3_dat4 */
			DRA7XX_CORE_IOPAD(0x3798, PIN_INPUT_PULLUP | MUX_MODE0) 	/* mmc3_dat5.mmc3_dat5 */
			DRA7XX_CORE_IOPAD(0x379c, PIN_INPUT_PULLUP | MUX_MODE0) 	/* mmc3_dat6.mmc3_dat6 */
			DRA7XX_CORE_IOPAD(0x37a0, PIN_INPUT_PULLUP | MUX_MODE0) 	/* mmc3_dat7.mmc3_dat7 */
		>;
	};

	mmc3_pins_sdr12: pinmux_mmc3_pins_sdr12 {
		pinctrl-single,pins = <
			DRA7XX_CORE_IOPAD(0x377c, PIN_INPUT_PULLUP | MUX_MODE0) 	/* mmc3_clk.mmc3_clk */
			DRA7XX_CORE_IOPAD(0x3780, PIN_INPUT_PULLUP | MUX_MODE0) 	/* mmc3_cmd.mmc3_cmd */
			DRA7XX_CORE_IOPAD(0x3784, PIN_INPUT_PULLUP | MUX_MODE0) 	/* mmc3_dat0.mmc3_dat0 */
			DRA7XX_CORE_IOPAD(0x3788, PIN_INPUT_PULLUP | MUX_MODE0) 	/* mmc3_dat1.mmc3_dat1 */
			DRA7XX_CORE_IOPAD(0x378c, PIN_INPUT_PULLUP | MUX_MODE0) 	/* mmc3_dat2.mmc3_dat2 */
			DRA7XX_CORE_IOPAD(0x3790, PIN_INPUT_PULLUP | MUX_MODE0) 	/* mmc3_dat3.mmc3_dat3 */
		>;
	};

	mmc3_pins_hs: pinmux_mmc3_pins_hs {
		pinctrl-single,pins = <
			DRA7XX_CORE_IOPAD(0x377c, PIN_INPUT_PULLUP | MUX_MODE0) 	/* mmc3_clk.mmc3_clk */
			DRA7XX_CORE_IOPAD(0x3780, PIN_INPUT_PULLUP | MUX_MODE0) 	/* mmc3_cmd.mmc3_cmd */
			DRA7XX_CORE_IOPAD(0x3784, PIN_INPUT_PULLUP | MUX_MODE0) 	/* mmc3_dat0.mmc3_dat0 */
			DRA7XX_CORE_IOPAD(0x3788, PIN_INPUT_PULLUP | MUX_MODE0) 	/* mmc3_dat1.mmc3_dat1 */
			DRA7XX_CORE_IOPAD(0x378c, PIN_INPUT_PULLUP | MUX_MODE0) 	/* mmc3_dat2.mmc3_dat2 */
			DRA7XX_CORE_IOPAD(0x3790, PIN_INPUT_PULLUP | MUX_MODE0) 	/* mmc3_dat3.mmc3_dat3 */
		>;
	};

	mmc3_pins_sdr25: pinmux_mmc3_pins_sdr25 {
		pinctrl-single,pins = <
			DRA7XX_CORE_IOPAD(0x377c, PIN_INPUT_PULLUP | MUX_MODE0) 	/* mmc3_clk.mmc3_clk */
			DRA7XX_CORE_IOPAD(0x3780, PIN_INPUT_PULLUP | MUX_MODE0) 	/* mmc3_cmd.mmc3_cmd */
			DRA7XX_CORE_IOPAD(0x3784, PIN_INPUT_PULLUP | MUX_MODE0) 	/* mmc3_dat0.mmc3_dat0 */
			DRA7XX_CORE_IOPAD(0x3788, PIN_INPUT_PULLUP | MUX_MODE0) 	/* mmc3_dat1.mmc3_dat1 */
			DRA7XX_CORE_IOPAD(0x378c, PIN_INPUT_PULLUP | MUX_MODE0) 	/* mmc3_dat2.mmc3_dat2 */
			DRA7XX_CORE_IOPAD(0x3790, PIN_INPUT_PULLUP | MUX_MODE0) 	/* mmc3_dat3.mmc3_dat3 */
		>;
	};

	mmc3_pins_sdr50: pinmux_mmc3_pins_sdr50 {
		pinctrl-single,pins = <
			DRA7XX_CORE_IOPAD(0x377c, PIN_INPUT_PULLUP | 1<<8 | MUX_MODE0) 	/* mmc3_clk.mmc3_clk */
			DRA7XX_CORE_IOPAD(0x3780, PIN_INPUT_PULLUP | 1<<8 | MUX_MODE0) 	/* mmc3_cmd.mmc3_cmd */
			DRA7XX_CORE_IOPAD(0x3784, PIN_INPUT_PULLUP | 1<<8 | MUX_MODE0) 	/* mmc3_dat0.mmc3_dat0 */
			DRA7XX_CORE_IOPAD(0x3788, PIN_INPUT_PULLUP | 1<<8 | MUX_MODE0) 	/* mmc3_dat1.mmc3_dat1 */
			DRA7XX_CORE_IOPAD(0x378c, PIN_INPUT_PULLUP | 1<<8 | MUX_MODE0) 	/* mmc3_dat2.mmc3_dat2 */
			DRA7XX_CORE_IOPAD(0x3790, PIN_INPUT_PULLUP | 1<<8 | MUX_MODE0) 	/* mmc3_dat3.mmc3_dat3 */
		>;
	};

	vout3_ds: pinmux_vout3_ds {
		pinctrl-single,pins = <
			DRA7XX_CORE_IOPAD(0x3464, 0x90003)
			DRA7XX_CORE_IOPAD(0x3460, 0x90003)
			DRA7XX_CORE_IOPAD(0x34bc, 0x90003)
			DRA7XX_CORE_IOPAD(0x3468, 0x90003)
			DRA7XX_CORE_IOPAD(0x3400, 0x90003) /*d0*/
			DRA7XX_CORE_IOPAD(0x3404, 0x90003) /*d1*/
			DRA7XX_CORE_IOPAD(0x3408, 0x90003)
			DRA7XX_CORE_IOPAD(0x340c, 0x90003)
			DRA7XX_CORE_IOPAD(0x3410, 0x90003)
			DRA7XX_CORE_IOPAD(0x3414, 0x90003)
			DRA7XX_CORE_IOPAD(0x3418, 0x90003)
			DRA7XX_CORE_IOPAD(0x341c, 0x90003)
			DRA7XX_CORE_IOPAD(0x3420, 0x90003)
			DRA7XX_CORE_IOPAD(0x3424, 0x90003)
			DRA7XX_CORE_IOPAD(0x3428, 0x90003)
			DRA7XX_CORE_IOPAD(0x342c, 0x90003)
			DRA7XX_CORE_IOPAD(0x3430, 0x90003)
			DRA7XX_CORE_IOPAD(0x3434, 0x90003)
			DRA7XX_CORE_IOPAD(0x3438, 0x90003)
			DRA7XX_CORE_IOPAD(0x343c, 0x90003)
			DRA7XX_CORE_IOPAD(0x3440, 0x90003)
			DRA7XX_CORE_IOPAD(0x3444, 0x90003)
			DRA7XX_CORE_IOPAD(0x3448, 0x90003)
			DRA7XX_CORE_IOPAD(0x344c, 0x90003)
			DRA7XX_CORE_IOPAD(0x3450, 0x90003)
			DRA7XX_CORE_IOPAD(0x3454, 0x90003)
			DRA7XX_CORE_IOPAD(0x3458, 0x90003)
			DRA7XX_CORE_IOPAD(0x345c, 0x90003) /*d23*/


			DRA7XX_CORE_IOPAD(0x346c, 0x2000e)/* lcd pwr gpio2_1 */
		>;
	};
	vout2_ds: pinmux_vout2_ds {
		pinctrl-single,pins = <
			DRA7XX_CORE_IOPAD(0x3564, 0x90104)
			DRA7XX_CORE_IOPAD(0x3560, 0x90104)
			DRA7XX_CORE_IOPAD(0x355c, 0x90104)
			DRA7XX_CORE_IOPAD(0x3558, 0x90104)
			/*DRA7XX_CORE_IOPAD(0x3558, 0x2000e) de*/
			DRA7XX_CORE_IOPAD(0x35c4, 0x90104) /*d0*/
			DRA7XX_CORE_IOPAD(0x35c0, 0x90104) /*d1*/
			DRA7XX_CORE_IOPAD(0x35bc, 0x90104)
			DRA7XX_CORE_IOPAD(0x35b8, 0x90104)
			DRA7XX_CORE_IOPAD(0x35b4, 0x90104)
			DRA7XX_CORE_IOPAD(0x35b0, 0x90104)
			DRA7XX_CORE_IOPAD(0x35ac, 0x90104)
			DRA7XX_CORE_IOPAD(0x35a8, 0x90104)
			DRA7XX_CORE_IOPAD(0x35a4, 0x90104)
			DRA7XX_CORE_IOPAD(0x35a0, 0x90104)
			DRA7XX_CORE_IOPAD(0x359c, 0x90104)
			DRA7XX_CORE_IOPAD(0x3598, 0x90104)
			DRA7XX_CORE_IOPAD(0x3594, 0x90104)
			DRA7XX_CORE_IOPAD(0x3590, 0x90104)
			DRA7XX_CORE_IOPAD(0x358c, 0x90104)
			DRA7XX_CORE_IOPAD(0x3588, 0x90104)
			DRA7XX_CORE_IOPAD(0x3584, 0x90104)
			DRA7XX_CORE_IOPAD(0x3580, 0x90104)
			DRA7XX_CORE_IOPAD(0x357c, 0x90104)
			DRA7XX_CORE_IOPAD(0x3578, 0x90104)
			DRA7XX_CORE_IOPAD(0x3574, 0x90104)
			DRA7XX_CORE_IOPAD(0x3570, 0x90104)
			DRA7XX_CORE_IOPAD(0x356c, 0x90104)
			DRA7XX_CORE_IOPAD(0x3568, 0x90104) /*d23*/

		>;
	};


	i2c3_pins_default: i2c3_pins_default {
		pinctrl-single,pins = <
			DRA7XX_CORE_IOPAD(0x34c0, 0x50008)
			DRA7XX_CORE_IOPAD(0x34c4, 0x50008)
		>;
	};

	i2c4_pins_default: i2c4_pins_default {
		pinctrl-single,pins = <
			DRA7XX_CORE_IOPAD(0x36b0, 0x5000a)
			DRA7XX_CORE_IOPAD(0x36ac, 0x5000a)
			DRA7XX_CORE_IOPAD(0x34d4, 0x6000E)/*tp int gpio2_27*/
		>;
	};

	tp_pin: pinmux_tp_pin {
		pinctrl-single,pins = <
			DRA7XX_CORE_IOPAD(0x34d4, 0x6000E)/*tp int gpio2_27*/
		>;
	};

	mcasp2_pins_default: mcasp2_pins_default {
		pinctrl-single,pins = <
			DRA7XX_CORE_IOPAD(0x3698, 0x50003)
			DRA7XX_CORE_IOPAD(0x36f4, 0x50000)
			DRA7XX_CORE_IOPAD(0x36f8, 0xd0000)
			DRA7XX_CORE_IOPAD(0x3704, 0x50000)
			DRA7XX_CORE_IOPAD(0x3708, 0x50000)
			DRA7XX_CORE_IOPAD(0x370c, 0xd0000)
			DRA7XX_CORE_IOPAD(0x3710, 0xd0000)
			DRA7XX_CORE_IOPAD(0x3694, 0x00009)/* ahclk_clkout2 */
		>;
	};

	mcasp3_pins_default: mcasp3_pins_default {
		pinctrl-single,pins = <
			DRA7XX_CORE_IOPAD(0x3728, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp3_fsx.mcasp3_fsx */
			DRA7XX_CORE_IOPAD(0x372c, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mcasp3_axr0.mcasp3_axr0 */
			DRA7XX_CORE_IOPAD(0x3730, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp3_axr1.mcasp3_axr1 */
		>;
	};

	mcasp3_pins_sleep: mcasp3_pins_sleep {
		pinctrl-single,pins = <
			DRA7XX_CORE_IOPAD(0x3728, PIN_INPUT | MUX_MODE15)
			DRA7XX_CORE_IOPAD(0x372c, PIN_INPUT | MUX_MODE15)
			DRA7XX_CORE_IOPAD(0x3730, PIN_INPUT | MUX_MODE15)
		>;
	};
	mcasp4_pins_default: mcasp4_pins_default {
		pinctrl-single,pins = <
			DRA7XX_CORE_IOPAD(0x3734, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp3_aclkx.mcasp3_aclkx */
			DRA7XX_CORE_IOPAD(0x3738, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp3_fsx.mcasp3_fsx */
			DRA7XX_CORE_IOPAD(0x373c, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mcasp3_axr0.mcasp3_axr0 */
			DRA7XX_CORE_IOPAD(0x3740, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp3_axr1.mcasp3_axr1 */
			DRA7XX_CORE_IOPAD(0x36a0, PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* xref_clk2.mcasp3_ahclkx */
		>;
	};

	mcasp4_pins_sleep: mcasp4_pins_sleep {
		pinctrl-single,pins = <
			DRA7XX_CORE_IOPAD(0x3734, PIN_INPUT | MUX_MODE15)
			DRA7XX_CORE_IOPAD(0x3738, PIN_INPUT | MUX_MODE15)
			DRA7XX_CORE_IOPAD(0x373c, PIN_INPUT | MUX_MODE15)
			DRA7XX_CORE_IOPAD(0x3740, PIN_INPUT | MUX_MODE15)
		>;
	};

	mcasp5_pins_default: mcasp5_pins_default {
		pinctrl-single,pins = <
			DRA7XX_CORE_IOPAD(0x3744, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp5_aclkx.mcasp5_aclkx*/
			DRA7XX_CORE_IOPAD(0x3748, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp5_fsx.mcasp5_fsx*/
			DRA7XX_CORE_IOPAD(0x374c, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mcasp5_axr0.mcasp5_axr0*/
			DRA7XX_CORE_IOPAD(0x3750, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp5_axr1.mcasp5_axr1*/
			DRA7XX_CORE_IOPAD(0x3694, PIN_OUTPUT_PULLDOWN | MUX_MODE4) /* xref_clk0.mcasp5_ahclkx*/
		>;
	};

	mcasp5_pins_sleep: mcasp5_pins_sleep {
		pinctrl-single,pins = <
			DRA7XX_CORE_IOPAD(0x3744, PIN_INPUT | MUX_MODE15)
			DRA7XX_CORE_IOPAD(0x3748, PIN_INPUT | MUX_MODE15)
			DRA7XX_CORE_IOPAD(0x374c, PIN_INPUT | MUX_MODE15)
			DRA7XX_CORE_IOPAD(0x3750, PIN_INPUT | MUX_MODE15)
			DRA7XX_CORE_IOPAD(0x3694, PIN_INPUT | MUX_MODE15)
		>;
	};

	mcasp6_pins_default: mcasp6_pins_default {
		pinctrl-single,pins = <
			DRA7XX_CORE_IOPAD(0x36dc, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mcasp1_axr10.mcasp6_aclkx*/
			DRA7XX_CORE_IOPAD(0x36e0, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mcasp1_axr11.mcasp6_fsx*/
			DRA7XX_CORE_IOPAD(0x36d4, PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mcasp1_axr8.mcasp6_axr0*/
			DRA7XX_CORE_IOPAD(0x36d8, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mcasp1_axr9.mcasp6_axr1*/
			DRA7XX_CORE_IOPAD(0x3698, PIN_OUTPUT_PULLDOWN | MUX_MODE4) /* xref_clk1.mcasp6_ahclkx*/
		>;
	};

	mcasp6_pins_sleep: mcasp6_pins_sleep {
		pinctrl-single,pins = <
			DRA7XX_CORE_IOPAD(0x36dc, PIN_INPUT | MUX_MODE15)
			DRA7XX_CORE_IOPAD(0x36e0, PIN_INPUT | MUX_MODE15)
			DRA7XX_CORE_IOPAD(0x36d4, PIN_INPUT | MUX_MODE15)
			DRA7XX_CORE_IOPAD(0x36d8, PIN_INPUT | MUX_MODE15)
			DRA7XX_CORE_IOPAD(0x3698, PIN_INPUT | MUX_MODE15)
		>;
	};

	mcspi1_pins_default: mcspi1_pins_default {
		pinctrl-single,pins = <
			DRA7XX_CORE_IOPAD(0x37a4, 0x50000)
			DRA7XX_CORE_IOPAD(0x37b0, 0x50000)
			DRA7XX_CORE_IOPAD(0x37ac, 0x50000)
			DRA7XX_CORE_IOPAD(0x37a8, 0x50000)
			DRA7XX_CORE_IOPAD(0x37b4, 0x6000e) /*gpio7_11 hi3599 flag*/
		>;
	};

	mcspi2_pins_default: mcspi2_pins_default {
		pinctrl-single,pins = <
			DRA7XX_CORE_IOPAD(0x37c0, 0x50000)
			DRA7XX_CORE_IOPAD(0x37c8, 0x50000)
			DRA7XX_CORE_IOPAD(0x37c4, 0x50000)
			DRA7XX_CORE_IOPAD(0x37cc, 0x50000)
		>;
	};

	uart1_pins_default: uart1_pins_default {
		pinctrl-single,pins = <
			DRA7XX_CORE_IOPAD(0x37e0, 0xd0000)
			/*DRA7XX_CORE_IOPAD(0x37ec, 0x20000)*/
		>;
	};

	uart4_pins_default: uart4_pins_default {
		pinctrl-single,pins = <
			DRA7XX_CORE_IOPAD(0x373c, 0x50004)
			DRA7XX_CORE_IOPAD(0x3740, 0x10004)
		>;
	};

	uart10_pins_default: uart10_pins_default {
		pinctrl-single,pins = <
			DRA7XX_CORE_IOPAD(0x379c, 0x50002) /*uart10 cts*/
			DRA7XX_CORE_IOPAD(0x37a0, 0x10002) /*uart10 rts*/
		>;
	};



	cpsw_pins_default: cpsw_pins_default {
		pinctrl-single,pins = <
			/* Slave at addr 0x0 */
			DRA7XX_CORE_IOPAD(0x3660, 0x50101) /*rgmii0_txd1 rmii0_rxd1*/
			DRA7XX_CORE_IOPAD(0x3664, 0x50101) /*rgmii0_txd0   rmii0_rxd0*/
			DRA7XX_CORE_IOPAD(0x367c, 0x10001) /*rgmii0_rxd0   rmii0_txd0*/
			DRA7XX_CORE_IOPAD(0x3678, 0x10001) /*rgmii0_rxd1   rmii0_txd1*/
			DRA7XX_CORE_IOPAD(0x365c, 0x50101) /*rgmii0_txd2   rmii0_rxer*/
			DRA7XX_CORE_IOPAD(0x3658, 0x50101) /*rgmii0_txd3   rmii0_crs*/
			DRA7XX_CORE_IOPAD(0x3674, 0x10001) /*rgmii0_rxd2   rmii0_txen*/

			/* Slave at addr 0x1 */
		>;
	};

	cpsw_pins_sleep: cpsw_pins_sleep {
		pinctrl-single,pins = <
			/* Slave 1 */
			DRA7XX_CORE_IOPAD(0x3660, PIN_INPUT | MUX_MODE15)
			DRA7XX_CORE_IOPAD(0x3664, PIN_INPUT | MUX_MODE15)
			DRA7XX_CORE_IOPAD(0x367c, PIN_INPUT | MUX_MODE15)
			DRA7XX_CORE_IOPAD(0x3678, PIN_INPUT | MUX_MODE15)
			DRA7XX_CORE_IOPAD(0x365c, PIN_INPUT | MUX_MODE15)
			DRA7XX_CORE_IOPAD(0x3658, PIN_INPUT | MUX_MODE15)
			DRA7XX_CORE_IOPAD(0x3674, PIN_INPUT | MUX_MODE15)

			/* Slave 2 */
		>;
	};

	davinci_mdio_pins_default: davinci_mdio_pins_default {
		pinctrl-single,pins = <
			/* MDIO */
			DRA7XX_CORE_IOPAD(0x363c, PIN_OUTPUT_PULLUP | MUX_MODE0)
			DRA7XX_CORE_IOPAD(0x3640, PIN_INPUT_PULLUP | MUX_MODE0)
		>;
	};

	davinci_mdio_pins_sleep: davinci_mdio_pins_sleep {
		pinctrl-single,pins = <
			DRA7XX_CORE_IOPAD(0x363c, PIN_INPUT | MUX_MODE15)
			DRA7XX_CORE_IOPAD(0x3640, PIN_INPUT | MUX_MODE15)
		>;
	};

	hdmi_pins: pinmux_hdmi_pins {
		pinctrl-single,pins = <
			DRA7XX_CORE_IOPAD(0x3808, PIN_INPUT | MUX_MODE1)	/* i2c2_sda.hdmi1_ddc_scl */
			DRA7XX_CORE_IOPAD(0x380c, PIN_INPUT | MUX_MODE1)	/* i2c2_scl.hdmi1_ddc_sda */
		>;
	};

	mmc4_pins_ds: pinmux_mmc4_pins_ds {
		pinctrl-single,pins = <
			DRA7XX_CORE_IOPAD(0x37e8, PIN_INPUT_PULLUP | MUX_MODE3)
			DRA7XX_CORE_IOPAD(0x37ec, PIN_INPUT_PULLUP | MUX_MODE3)
			DRA7XX_CORE_IOPAD(0x37f0, PIN_INPUT_PULLUP | MUX_MODE3)
			DRA7XX_CORE_IOPAD(0x37f4, PIN_INPUT_PULLUP | MUX_MODE3)
			DRA7XX_CORE_IOPAD(0x37f8, PIN_INPUT_PULLUP | MUX_MODE3)
			DRA7XX_CORE_IOPAD(0x37fc, PIN_INPUT_PULLUP | MUX_MODE3)
		>;
	};

	mmc4_pins_default: mmc4_pins_default {
		pinctrl-single,pins = <
			DRA7XX_CORE_IOPAD(0x37e8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart1_ctsn.mmc4_clk */
			DRA7XX_CORE_IOPAD(0x37ec, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart1_rtsn.mmc4_cmd */
			DRA7XX_CORE_IOPAD(0x37f0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_rxd.mmc4_dat0 */
			DRA7XX_CORE_IOPAD(0x37f4, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_txd.mmc4_dat1 */
			DRA7XX_CORE_IOPAD(0x37f8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_ctsn.mmc4_dat2 */
			DRA7XX_CORE_IOPAD(0x37fc, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_rtsn.mmc4_dat3 */
		>;
	};

	mmc4_pins_hs: mmc4_pins_hs {
		pinctrl-single,pins = <
			DRA7XX_CORE_IOPAD(0x37e8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart1_ctsn.mmc4_clk */
			DRA7XX_CORE_IOPAD(0x37ec, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart1_rtsn.mmc4_cmd */
			DRA7XX_CORE_IOPAD(0x37f0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_rxd.mmc4_dat0 */
			DRA7XX_CORE_IOPAD(0x37f4, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_txd.mmc4_dat1 */
			DRA7XX_CORE_IOPAD(0x37f8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_ctsn.mmc4_dat2 */
			DRA7XX_CORE_IOPAD(0x37fc, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_rtsn.mmc4_dat3 */
		>;
	};

	mmc4_pins_sdr12: mmc4_pins_sdr12 {
		pinctrl-single,pins = <
			DRA7XX_CORE_IOPAD(0x37e8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart1_ctsn.mmc4_clk */
			DRA7XX_CORE_IOPAD(0x37ec, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart1_rtsn.mmc4_cmd */
			DRA7XX_CORE_IOPAD(0x37f0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_rxd.mmc4_dat0 */
			DRA7XX_CORE_IOPAD(0x37f4, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_txd.mmc4_dat1 */
			DRA7XX_CORE_IOPAD(0x37f8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_ctsn.mmc4_dat2 */
			DRA7XX_CORE_IOPAD(0x37fc, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_rtsn.mmc4_dat3 */
		>;
	};

	mmc4_pins_sdr25: mmc4_pins_sdr25 {
		pinctrl-single,pins = <
			DRA7XX_CORE_IOPAD(0x37e8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart1_ctsn.mmc4_clk */
			DRA7XX_CORE_IOPAD(0x37ec, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart1_rtsn.mmc4_cmd */
			DRA7XX_CORE_IOPAD(0x37f0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_rxd.mmc4_dat0 */
			DRA7XX_CORE_IOPAD(0x37f4, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_txd.mmc4_dat1 */
			DRA7XX_CORE_IOPAD(0x37f8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_ctsn.mmc4_dat2 */
			DRA7XX_CORE_IOPAD(0x37fc, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_rtsn.mmc4_dat3 */
		>;
	};
};

&dra7_iodelay_core {
	mmc1_iodelay_ddr50_conf: mmc1_iodelay_ddr50_conf {
		pinctrl-pin-array = <
			0x618 A_DELAY_PS(0) G_DELAY_PS(0)		/* CFG_MMC1_CLK_IN */
			0x624 A_DELAY_PS(0) G_DELAY_PS(0)		/* CFG_MMC1_CMD_IN */
			0x630 A_DELAY_PS(495) G_DELAY_PS(0)	/* CFG_MMC1_DAT0_IN */
			0x63C A_DELAY_PS(116) G_DELAY_PS(0)	/* CFG_MMC1_DAT1_IN */
			0x648 A_DELAY_PS(117) G_DELAY_PS(0)	/* CFG_MMC1_DAT2_IN */
			0x654 A_DELAY_PS(32) G_DELAY_PS(0)	/* CFG_MMC1_DAT3_IN */
			0x620 A_DELAY_PS(1224) G_DELAY_PS(0)	/* CFG_MMC1_CLK_OUT */
			0x62C A_DELAY_PS(0) G_DELAY_PS(0)		/* CFG_MMC1_CMD_OUT */
			0x638 A_DELAY_PS(44) G_DELAY_PS(0)	/* CFG_MMC1_DAT0_OUT */
			0x644 A_DELAY_PS(64) G_DELAY_PS(0)	/* CFG_MMC1_DAT1_OUT */
			0x650 A_DELAY_PS(79) G_DELAY_PS(0)	/* CFG_MMC1_DAT2_OUT */
			0x65C A_DELAY_PS(87) G_DELAY_PS(0)	/* CFG_MMC1_DAT3_OUT */
			0x628 A_DELAY_PS(0) G_DELAY_PS(0)		/* CFG_MMC1_CMD_OEN */
			0x634 A_DELAY_PS(0) G_DELAY_PS(0)		/* CFG_MMC1_DAT0_OEN */
			0x640 A_DELAY_PS(0) G_DELAY_PS(0)		/* CFG_MMC1_DAT1_OEN */
			0x64C A_DELAY_PS(0) G_DELAY_PS(0)		/* CFG_MMC1_DAT2_OEN */
			0x658 A_DELAY_PS(0) G_DELAY_PS(0)		/* CFG_MMC1_DAT3_OEN */
		>;
	};

	mmc1_iodelay_sdr104_conf: mmc1_iodelay_sdr104_conf {
		pinctrl-pin-array = <
			0x620 A_DELAY_PS(520) G_DELAY_PS(320)	/* CFG_MMC1_CLK_OUT */
			0x62c A_DELAY_PS(0) G_DELAY_PS(0)		/* CFG_MMC1_CMD_OUT */
			0x638 A_DELAY_PS(40) G_DELAY_PS(0)	/* CFG_MMC1_DAT0_OUT */
			0x644 A_DELAY_PS(83) G_DELAY_PS(0)	/* CFG_MMC1_DAT1_OUT */
			0x650 A_DELAY_PS(98) G_DELAY_PS(0)	/* CFG_MMC1_DAT2_OUT */
			0x65c A_DELAY_PS(106) G_DELAY_PS(0)	/* CFG_MMC1_DAT3_OUT */
			0x628 A_DELAY_PS(51) G_DELAY_PS(0)	/* CFG_MMC1_CMD_OEN */
			0x634 A_DELAY_PS(0) G_DELAY_PS(0)		/* CFG_MMC1_DAT0_OEN */
			0x640 A_DELAY_PS(363) G_DELAY_PS(0)	/* CFG_MMC1_DAT1_OEN */
			0x64c A_DELAY_PS(199) G_DELAY_PS(0)	/* CFG_MMC1_DAT2_OEN */
			0x658 A_DELAY_PS(273) G_DELAY_PS(0)	/* CFG_MMC1_DAT3_OEN */
		>;
	};

	mmc2_iodelay_ddr_1_8v_conf: mmc2_iodelay_ddr_1_8v_conf {
		pinctrl-pin-array = <
			0x18c A_DELAY_PS(0) G_DELAY_PS(0)		/* CFG_GPMC_A19_IN */
			0x1a4 A_DELAY_PS(121) G_DELAY_PS(0)	/* CFG_GPMC_A20_IN */
			0x1b0 A_DELAY_PS(0) G_DELAY_PS(0)		/* CFG_GPMC_A21_IN */
			0x1bc A_DELAY_PS(20) G_DELAY_PS(0)	/* CFG_GPMC_A22_IN */
			0x1c8 A_DELAY_PS(108) G_DELAY_PS(0)	/* CFG_GPMC_A23_IN */
			0x1d4 A_DELAY_PS(31) G_DELAY_PS(0)	/* CFG_GPMC_A24_IN */
			0x1e0 A_DELAY_PS(0) G_DELAY_PS(0)		/* CFG_GPMC_A25_IN */
			0x1ec A_DELAY_PS(24) G_DELAY_PS(0)	/* CFG_GPMC_A26_IN */
			0x1f8 A_DELAY_PS(0) G_DELAY_PS(0)		/* CFG_GPMC_A27_IN */
			0x360 A_DELAY_PS(0) G_DELAY_PS(0)		/* CFG_GPMC_CS1_IN */
			0x194 A_DELAY_PS(152) G_DELAY_PS(0)	/* CFG_GPMC_A19_OUT */
			0x1ac A_DELAY_PS(206) G_DELAY_PS(0)	/* CFG_GPMC_A20_OUT */
			0x1b8 A_DELAY_PS(78) G_DELAY_PS(0)	/* CFG_GPMC_A21_OUT */
			0x1c4 A_DELAY_PS(2) G_DELAY_PS(0)		/* CFG_GPMC_A22_OUT */
			0x1d0 A_DELAY_PS(266) G_DELAY_PS(0)	/* CFG_GPMC_A23_OUT */
			0x1dc A_DELAY_PS(0) G_DELAY_PS(0)		/* CFG_GPMC_A24_OUT */
			0x1e8 A_DELAY_PS(0) G_DELAY_PS(0)		/* CFG_GPMC_A25_OUT */
			0x1f4 A_DELAY_PS(43) G_DELAY_PS(0)	/* CFG_GPMC_A26_OUT */
			0x200 A_DELAY_PS(0) G_DELAY_PS(0)		/* CFG_GPMC_A27_OUT */
			0x368 A_DELAY_PS(0) G_DELAY_PS(0)		/* CFG_GPMC_CS1_OUT */
			0x190 A_DELAY_PS(0) G_DELAY_PS(0)		/* CFG_GPMC_A19_OEN */
			0x1a8 A_DELAY_PS(0) G_DELAY_PS(0)		/* CFG_GPMC_A20_OEN */
			0x1b4 A_DELAY_PS(0) G_DELAY_PS(0)		/* CFG_GPMC_A21_OEN */
			0x1c0 A_DELAY_PS(0) G_DELAY_PS(0)		/* CFG_GPMC_A22_OEN */
			0x1d8 A_DELAY_PS(0) G_DELAY_PS(0)		/* CFG_GPMC_A24_OEN */
			0x1e4 A_DELAY_PS(0) G_DELAY_PS(0)		/* CFG_GPMC_A25_OEN */
			0x1f0 A_DELAY_PS(0) G_DELAY_PS(0)		/* CFG_GPMC_A26_OEN */
			0x1fc A_DELAY_PS(0) G_DELAY_PS(0)		/* CFG_GPMC_A27_OEN */
			0x364 A_DELAY_PS(0) G_DELAY_PS(0)		/* CFG_GPMC_CS1_OEN */
		>;
	};

	mmc3_iodelay_sdr50_rev20_conf: mmc3_iodelay_sdr50_rev20_conf {
		pinctrl-single,pins = <
			0x678 (A_DELAY_PS(1085) | G_DELAY_PS(21)) 	/* CFG_MMC3_CLK_IN */
			0x680 (A_DELAY_PS(1269) | G_DELAY_PS(0)) 	/* CFG_MMC3_CLK_OUT */
			0x684 (A_DELAY_PS(0) | G_DELAY_PS(0)) 	/* CFG_MMC3_CMD_IN */
			0x688 (A_DELAY_PS(128) | G_DELAY_PS(0)) 	/* CFG_MMC3_CMD_OEN */
			0x68C (A_DELAY_PS(98) | G_DELAY_PS(0)) 	/* CFG_MMC3_CMD_OUT */
			0x690 (A_DELAY_PS(0) | G_DELAY_PS(0)) 	/* CFG_MMC3_DAT0_IN */
			0x694 (A_DELAY_PS(362) | G_DELAY_PS(0)) 	/* CFG_MMC3_DAT0_OEN */
			0x698 (A_DELAY_PS(0) | G_DELAY_PS(0)) 	/* CFG_MMC3_DAT0_OUT */
			0x69C (A_DELAY_PS(7) | G_DELAY_PS(0)) 	/* CFG_MMC3_DAT1_IN */
			0x6A0 (A_DELAY_PS(333) | G_DELAY_PS(0)) 	/* CFG_MMC3_DAT1_OEN */
			0x6A4 (A_DELAY_PS(0) | G_DELAY_PS(0)) 	/* CFG_MMC3_DAT1_OUT */
			0x6A8 (A_DELAY_PS(0) | G_DELAY_PS(0)) 	/* CFG_MMC3_DAT2_IN */
			0x6AC (A_DELAY_PS(402) | G_DELAY_PS(0)) 	/* CFG_MMC3_DAT2_OEN */
			0x6B0 (A_DELAY_PS(0) | G_DELAY_PS(0)) 	/* CFG_MMC3_DAT2_OUT */
			0x6B4 (A_DELAY_PS(203) | G_DELAY_PS(0)) 	/* CFG_MMC3_DAT3_IN */
			0x6B8 (A_DELAY_PS(549) | G_DELAY_PS(0)) 	/* CFG_MMC3_DAT3_OEN */
			0x6BC (A_DELAY_PS(1) | G_DELAY_PS(0)) 	/* CFG_MMC3_DAT3_OUT */
		>;
	};

	mmc4_iodelay_ds_rev11_conf: mmc4_iodelay_ds_rev11_conf {
		pinctrl-pin-array = <
			0x840 A_DELAY_PS(0) G_DELAY_PS(0)		/* CFG_UART1_CTSN_IN */
			0x848 A_DELAY_PS(0) G_DELAY_PS(0)		/* CFG_UART1_CTSN_OUT */
			0x84c A_DELAY_PS(96) G_DELAY_PS(0)	/* CFG_UART1_RTSN_IN */
			0x850 A_DELAY_PS(0) G_DELAY_PS(0)		/* CFG_UART1_RTSN_OEN */
			0x854 A_DELAY_PS(0) G_DELAY_PS(0)		/* CFG_UART1_RTSN_OUT */
			0x870 A_DELAY_PS(582) G_DELAY_PS(0)	/* CFG_UART2_CTSN_IN */
			0x874 A_DELAY_PS(0) G_DELAY_PS(0)		/* CFG_UART2_CTSN_OEN */
			0x878 A_DELAY_PS(0) G_DELAY_PS(0)		/* CFG_UART2_CTSN_OUT */
			0x87c A_DELAY_PS(391) G_DELAY_PS(0)	/* CFG_UART2_RTSN_IN */
			0x880 A_DELAY_PS(0) G_DELAY_PS(0)		/* CFG_UART2_RTSN_OEN */
			0x884 A_DELAY_PS(0) G_DELAY_PS(0)		/* CFG_UART2_RTSN_OUT */
			0x888 A_DELAY_PS(561) G_DELAY_PS(0)	/* CFG_UART2_RXD_IN */
			0x88c A_DELAY_PS(0) G_DELAY_PS(0)		/* CFG_UART2_RXD_OEN */
			0x890 A_DELAY_PS(0) G_DELAY_PS(0)		/* CFG_UART2_RXD_OUT */
			0x894 A_DELAY_PS(588) G_DELAY_PS(0)	/* CFG_UART2_TXD_IN */
			0x898 A_DELAY_PS(0) G_DELAY_PS(0)		/* CFG_UART2_TXD_OEN */
			0x89c A_DELAY_PS(0) G_DELAY_PS(0)		/* CFG_UART2_TXD_OUT */
		>;
	};

	mmc4_iodelay_ds_rev20_conf: mmc4_iodelay_ds_rev20_conf {
		pinctrl-pin-array = <
			0x840 A_DELAY_PS(0) G_DELAY_PS(0)		/* CFG_UART1_CTSN_IN */
			0x848 A_DELAY_PS(0) G_DELAY_PS(0)		/* CFG_UART1_CTSN_OUT */
			0x84c A_DELAY_PS(307) G_DELAY_PS(0)	/* CFG_UART1_RTSN_IN */
			0x850 A_DELAY_PS(0) G_DELAY_PS(0)		/* CFG_UART1_RTSN_OEN */
			0x854 A_DELAY_PS(0) G_DELAY_PS(0)		/* CFG_UART1_RTSN_OUT */
			0x870 A_DELAY_PS(785) G_DELAY_PS(0)	/* CFG_UART2_CTSN_IN */
			0x874 A_DELAY_PS(0) G_DELAY_PS(0)		/* CFG_UART2_CTSN_OEN */
			0x878 A_DELAY_PS(0) G_DELAY_PS(0)		/* CFG_UART2_CTSN_OUT */
			0x87c A_DELAY_PS(613) G_DELAY_PS(0)	/* CFG_UART2_RTSN_IN */
			0x880 A_DELAY_PS(0) G_DELAY_PS(0)		/* CFG_UART2_RTSN_OEN */
			0x884 A_DELAY_PS(0) G_DELAY_PS(0)		/* CFG_UART2_RTSN_OUT */
			0x888 A_DELAY_PS(683) G_DELAY_PS(0)	/* CFG_UART2_RXD_IN */
			0x88c A_DELAY_PS(0) G_DELAY_PS(0)		/* CFG_UART2_RXD_OEN */
			0x890 A_DELAY_PS(0) G_DELAY_PS(0)		/* CFG_UART2_RXD_OUT */
			0x894 A_DELAY_PS(835) G_DELAY_PS(0)	/* CFG_UART2_TXD_IN */
			0x898 A_DELAY_PS(0) G_DELAY_PS(0)		/* CFG_UART2_TXD_OEN */
			0x89c A_DELAY_PS(0) G_DELAY_PS(0)		/* CFG_UART2_TXD_OUT */
		>;
	};

	mmc4_iodelay_sdr12_hs_sdr25_rev11_conf: mmc4_iodelay_sdr12_hs_sdr25_rev11_conf {
		pinctrl-pin-array = <
			0x840 A_DELAY_PS(0) G_DELAY_PS(0)		/* CFG_UART1_CTSN_IN */
			0x848 A_DELAY_PS(2651) G_DELAY_PS(0)	/* CFG_UART1_CTSN_OUT */
			0x84c A_DELAY_PS(1572) G_DELAY_PS(0)	/* CFG_UART1_RTSN_IN */
			0x850 A_DELAY_PS(0) G_DELAY_PS(0)		/* CFG_UART1_RTSN_OEN */
			0x854 A_DELAY_PS(0) G_DELAY_PS(0)		/* CFG_UART1_RTSN_OUT */
			0x870 A_DELAY_PS(1913) G_DELAY_PS(0)	/* CFG_UART2_CTSN_IN */
			0x874 A_DELAY_PS(0) G_DELAY_PS(0)		/* CFG_UART2_CTSN_OEN */
			0x878 A_DELAY_PS(0) G_DELAY_PS(0)		/* CFG_UART2_CTSN_OUT */
			0x87c A_DELAY_PS(1721) G_DELAY_PS(0)	/* CFG_UART2_RTSN_IN */
			0x880 A_DELAY_PS(0) G_DELAY_PS(0)		/* CFG_UART2_RTSN_OEN */
			0x884 A_DELAY_PS(0) G_DELAY_PS(0)		/* CFG_UART2_RTSN_OUT */
			0x888 A_DELAY_PS(1891) G_DELAY_PS(0)	/* CFG_UART2_RXD_IN */
			0x88c A_DELAY_PS(0) G_DELAY_PS(0)		/* CFG_UART2_RXD_OEN */
			0x890 A_DELAY_PS(0) G_DELAY_PS(0)		/* CFG_UART2_RXD_OUT */
			0x894 A_DELAY_PS(1919) G_DELAY_PS(0)	/* CFG_UART2_TXD_IN */
			0x898 A_DELAY_PS(0) G_DELAY_PS(0)		/* CFG_UART2_TXD_OEN */
			0x89c A_DELAY_PS(0) G_DELAY_PS(0)		/* CFG_UART2_TXD_OUT */
		>;
	};

	mmc4_iodelay_sdr12_hs_sdr25_rev20_conf: mmc4_iodelay_sdr12_hs_sdr25_rev20_conf {
		pinctrl-pin-array = <
			0x840 A_DELAY_PS(0) G_DELAY_PS(0)		/* CFG_UART1_CTSN_IN */
			0x848 A_DELAY_PS(1147) G_DELAY_PS(0)	/* CFG_UART1_CTSN_OUT */
			0x84c A_DELAY_PS(1834) G_DELAY_PS(0)	/* CFG_UART1_RTSN_IN */
			0x850 A_DELAY_PS(0) G_DELAY_PS(0)		/* CFG_UART1_RTSN_OEN */
			0x854 A_DELAY_PS(0) G_DELAY_PS(0)		/* CFG_UART1_RTSN_OUT */
			0x870 A_DELAY_PS(2165) G_DELAY_PS(0)	/* CFG_UART2_CTSN_IN */
			0x874 A_DELAY_PS(0) G_DELAY_PS(0)		/* CFG_UART2_CTSN_OEN */
			0x878 A_DELAY_PS(0) G_DELAY_PS(0)		/* CFG_UART2_CTSN_OUT */
			0x87c A_DELAY_PS(1929) G_DELAY_PS(64)	/* CFG_UART2_RTSN_IN */
			0x880 A_DELAY_PS(0) G_DELAY_PS(0)		/* CFG_UART2_RTSN_OEN */
			0x884 A_DELAY_PS(0) G_DELAY_PS(0)		/* CFG_UART2_RTSN_OUT */
			0x888 A_DELAY_PS(1935) G_DELAY_PS(128)	/* CFG_UART2_RXD_IN */
			0x88c A_DELAY_PS(0) G_DELAY_PS(0)		/* CFG_UART2_RXD_OEN */
			0x890 A_DELAY_PS(0) G_DELAY_PS(0)		/* CFG_UART2_RXD_OUT */
			0x894 A_DELAY_PS(2172) G_DELAY_PS(44)	/* CFG_UART2_TXD_IN */
			0x898 A_DELAY_PS(0) G_DELAY_PS(0)		/* CFG_UART2_TXD_OEN */
			0x89c A_DELAY_PS(0) G_DELAY_PS(0)		/* CFG_UART2_TXD_OUT */
		>;
	};
};

&mmc1 {
	pinctrl-names = "default", "hs";
	pinctrl-0 = <&mmc1_pins_default>;
	pinctrl-1 = <&mmc1_pins_hs>;
	/delete-property/ vmmc-supply;
	/delete-property/ vmmc_aux-supply;
	vmmc-supply = <&vsys_3v3>;
	cd-gpios = <&gpio6 27 0>; /* gpio 219 */
	wp-gpios = <&gpio6 28 0>; /* gpio 220 */
};

&mmc2 {
	//pinctrl-names = "default", "hs", "ddr_1_8v";
	pinctrl-names = "default", "hs";
	pinctrl-0 = <&mmc2_pins_default>;
	pinctrl-1 = <&mmc2_pins_hs>;
	//pinctrl-2 = <&mmc2_pins_ddr_1_8v &mmc2_iodelay_ddr_1_8v_conf>;
    /delete-property/ cd-gpios;
    /delete-property/ vmmc-supply;
    /delete-property/ vmmc_aux-supply;
    /delete-property/ mmc-ddr-1_8v;
    /delete-property/ no-1-8-v;
    vmmc-supply = <&vsys_3v3>;
    ti,non-removable;
	bus-width = <8>;
	max-frequency = <96000000>;
};

&mmc3 {
	//pinctrl-names = "default", "hs", "sdr12", "sdr25", "sdr50";
	pinctrl-names = "default", "hs";
	status = "okay";
	pinctrl-0 = <&mmc3_pins_ds>;
	pinctrl-1 = <&mmc3_pins_hs>;
	//pinctrl-2 = <&mmc3_pins_sdr12>;
	//pinctrl-3 = <&mmc3_pins_sdr25>;
	//pinctrl-4 = <&mmc3_pins_sdr50 &mmc3_iodelay_sdr50_rev20_conf>;
	/delete-property/ vmmc-supply;
	/delete-property/ vmmc_aux-supply;
	/delete-property/ mmc-ddr-1_8v;
	/delete-property/ no-1-8-v;
	/delete-property/ sd-uhs-sdr12;
	/delete-property/ sd-uhs-sdr25;
	/delete-property/ sd-uhs-sdr50;
	/delete-property/ ti,non-removable;
	//cd-gpios = <&gpio1 15 1>;
	vmmc-supply = <&emmcex_oe>;
	bus-width = <8>;
	max-frequency = <96000000>;
};

&mmc4 {
	pinctrl-names = "default";
	status = "okay";
	pinctrl-0 = <&mmc4_pins_ds>;
	vmmc-supply = <&vmmcwl_fixed>;
	ti,non-removable;
	ti,needs-special-hs-handling;
	cap-power-off-card;
	keep-power-in-suspend;

	#address-cells = <1>;
	#size-cells = <0>;
	wlcore: wlcore@0 {
		compatible = "ti,wl1807";
		reg = <2>;
		interrupt-parent = <&gpio5>;
		interrupts = <17 IRQ_TYPE_LEVEL_HIGH>;
	};
};

/*&mmc4 {
	status = "okay";
	vmmc-supply = <&vmmcwl_fixed>;
	bus-width = <4>;
	cap-power-off-card;
	keep-power-in-suspend;
	ti,non-removable;
	max-frequency = <400000>;

	pinctrl-names = "default-rev11", "default", "hs-rev11", "hs", "sdr12-rev11", "sdr12", "sdr25-rev11", "sdr25";
	//pinctrl-names = "default";
	pinctrl-0 = <&mmc4_pins_default &mmc4_iodelay_ds_rev11_conf>;
	pinctrl-1 = <&mmc4_pins_default &mmc4_iodelay_ds_rev20_conf>;
	pinctrl-2 = <&mmc4_pins_hs &mmc4_iodelay_sdr12_hs_sdr25_rev11_conf>;
	pinctrl-3 = <&mmc4_pins_hs &mmc4_iodelay_sdr12_hs_sdr25_rev20_conf>;
	pinctrl-4 = <&mmc4_pins_sdr12 &mmc4_iodelay_sdr12_hs_sdr25_rev11_conf>;
	pinctrl-5 = <&mmc4_pins_sdr12 &mmc4_iodelay_sdr12_hs_sdr25_rev20_conf>;
	pinctrl-6 = <&mmc4_pins_sdr25 &mmc4_iodelay_sdr12_hs_sdr25_rev11_conf>;
	pinctrl-7 = <&mmc4_pins_sdr25 &mmc4_iodelay_sdr12_hs_sdr25_rev20_conf>;

	#address-cells = <1>;
	#size-cells = <0>;
	wlcore: wlcore@2 {
		compatible = "ti,wl1807";
		reg = <2>;
		interrupt-parent = <&gpio5>;
		interrupts = <17 IRQ_TYPE_LEVEL_HIGH>;
	};
};*/

&usb2_phy1 {
	phy-supply = <&vsys_3v3>;
};

&usb2_phy2 {
	phy-supply = <&vsys_3v3>;
};

&usb1 {
	//dr_mode = "otg";
	dr_mode = "host";
};

&usb2 {
	dr_mode = "host";
};

&omap_dwc3_1 {
	extcon = <&extcon_usb1>;
};

&omap_dwc3_2 {
	extcon = <&extcon_usb2>;
};

&cpu0 {
	vdd-supply = <&lp8733_buck0_reg>;
};

&ov2659_1 {
	remote-endpoint = <&vin1b>;
};

&vin1b {
	status = "okay";

	endpoint@2 {
		slave-mode;
		remote-endpoint = <&ov2659_1>;
	};
};

&vip1 {
	status = "okay";
};

&mailbox5 {
	status = "okay";
	mbox_ipu1_ipc3x: mbox_ipu1_ipc3x {
		status = "okay";
	};
	mbox_dsp1_ipc3x: mbox_dsp1_ipc3x {
		status = "okay";
	};
};

&mailbox6 {
	status = "okay";
	mbox_ipu2_ipc3x: mbox_ipu2_ipc3x {
		status = "okay";
	};
};

&mmu0_dsp1 {
	status = "okay";
};

&mmu1_dsp1 {
	status = "okay";
};

&mmu_ipu1 {
	status = "okay";
};

&mmu_ipu2 {
	status = "okay";
};

&ipu2 {
	//status = "disable";
	status = "okay";
	memory-region = <&ipu2_cma_pool>;
	mboxes = <&mailbox6 &mbox_ipu2_ipc3x>;
	timers = <&timer3>;
	watchdog-timers = <&timer4>, <&timer9>;
};

&ipu1 {
	status = "okay";
	memory-region = <&ipu1_cma_pool>;
	mboxes = <&mailbox5 &mbox_ipu1_ipc3x>;
	timers = <&timer11>;
	watchdog-timers = <&timer7>, <&timer8>;
};

&dsp1 {
	status = "okay";
	memory-region = <&dsp1_cma_pool>;
	mboxes = <&mailbox5 &mbox_dsp1_ipc3x>;
	timers = <&timer5>;
	watchdog-timers = <&timer10>;
};

&dss {
	pinctrl-names = "default";
	//pinctrl-0 = <&vout2_ds>;
	pinctrl-0 = <&vout3_ds>;
};

&pruss1_mdio {
	reset-gpios = <&gpio5 8 GPIO_ACTIVE_LOW>;
	reset-delay-us = <2>;   /* PHY datasheet states 1uS min */
	pruss1_eth0_phy: ethernet-phy@0 {
		reg = <0>;
		interrupt-parent = <&gpio3>;
		interrupts = <28 IRQ_TYPE_EDGE_FALLING>;
	};

	pruss1_eth1_phy: ethernet-phy@1 {
		reg = <1>;
		interrupt-parent = <&gpio3>;
		interrupts = <29 IRQ_TYPE_EDGE_FALLING>;
	};
};

&pruss2_mdio {
	status = "disabled";
	reset-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
	reset-delay-us = <2>;   /* PHY datasheet states 1uS min */
};

&epwmss1 {
	status = "okay";
};

&ehrpwm1 {
	status = "okay";
};

&dss {
	vdda_video-supply = <&vsys_3v3>;//fixed later pmic
	ports {
        /delete-node/ port@0;
		port@2 {
			reg = <2>;

			dpi_out: endpoint {
				remote-endpoint = <&lcd_in>;
				data-lines = <24>;
			};
		};
    };
};

&hdmi {
	vdda-supply = <&vsys_1v8>;//fixed later pmic
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&hdmi_pins>;

	port {
		hdmi_out: endpoint {
			remote-endpoint = <&hdmi_connector_in>;
		};
	};
};

&hdmi0 {
    status = "disabled";
	pinctrl-names = "default";
	//pinctrl-0 = <&hdmi_conn_pins>;
	//hpd-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;
		port {
			hdmi_connector_in: endpoint {
				remote-endpoint = <&hdmi_out>;
			};
		};
};
&cal {
	status = "okay";
};

/*
&csi2_0 {
	csi2_phy0: endpoint@0 {
		slave-mode;
		remote-endpoint = <&csi2_cam0>;
	};
};
*/

&dcan1 {
	status = "disabled";
};

&dss {
       ti,no-reset-on-init;
       ti,no-idle-on-init;
       ti,no-idle;
       dispc@58001000 {
               ti,no-reset-on-init;
               ti,no-idle-on-init;
               ti,no-idle;
       };
};

&gpio6 {
       ti,no-reset-on-init;
};

    config.bld file

    Fullscreen 4861.config.bld.txt Download 
    /*
 * Copyright (c) 2013-2015, Texas Instruments Incorporated
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * *  Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 *
 * *  Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 *
 * *  Neither the name of Texas Instruments Incorporated nor the names of
 *    its contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */

/*
 *  ======== config.bld ========
 *
 */
var Build = xdc.useModule('xdc.bld.BuildEnvironment');

/*  Memory Map for ti.platforms.evmDRA7XX:dsp1 and ti.platforms.evmDRA7XX:dsp2
 *
 *  --- External Memory ---
 *  Virtual     Physical        Size            Comment
 *  ------------------------------------------------------------------------
 *  9500_4000   ????_????    10_0000  (  ~1 MB) EXT_CODE
 *  9510_0000   ????_????    10_0000  (   1 MB) EXT_DATA
 *  9520_0000   ????_????    30_0000  (   3 MB) EXT_HEAP
 *  9F00_0000   9F00_0000     6_0000  ( 384 kB) TRACE_BUF
 *  9F06_0000   9F06_0000     1_0000  (  64 kB) EXC_DATA
 *  9F07_0000   9F07_0000     2_0000  ( 128 kB) PM_DATA (Power mgmt)
 */
var evmDRA7XX_ExtMemMapDsp = {
    EXT_CODE: {
        name: "EXT_CODE",
        base: 0x95000000,
        len:  0x00100000,
        space: "code",
        access: "RWX"
    },
    EXT_DATA: {
        name: "EXT_DATA",
        base: 0x95100000,
        len:  0x00500000,
        space: "data",
        access: "RW"
    },
    EXT_HEAP: {
        name: "EXT_HEAP",
        base: 0x95600000,
        len:  0x00300000,
        space: "data",
        access: "RW"
    },
    TRACE_BUF: {
        name: "TRACE_BUF",
        base: 0x9F000000,
        len:  0x00060000,
        space: "data",
        access: "RW"
    },
    EXC_DATA: {
        name: "EXC_DATA",
        base: 0x9F060000,
        len:  0x00010000,
        space: "data",
        access: "RW"
    },
    PM_DATA: {
        name: "PM_DATA",
        base: 0x9F070000,
        len:  0x00020000,
        space: "data",
        access: "RWX"  /* should this have execute perm? */
    },
};

Build.platformTable["ti.platforms.evmDRA7XX:dsp1"] = {
    externalMemoryMap: [
        [ "EXT_CODE", evmDRA7XX_ExtMemMapDsp.EXT_CODE ],
        [ "EXT_DATA", evmDRA7XX_ExtMemMapDsp.EXT_DATA ],
        [ "EXT_HEAP", evmDRA7XX_ExtMemMapDsp.EXT_HEAP ],
        [ "TRACE_BUF", evmDRA7XX_ExtMemMapDsp.TRACE_BUF ],
        [ "EXC_DATA", evmDRA7XX_ExtMemMapDsp.EXC_DATA ],
        [ "PM_DATA", evmDRA7XX_ExtMemMapDsp.PM_DATA ],
    ],
    codeMemory: "EXT_CODE",
    dataMemory: "EXT_DATA",
    stackMemory: "EXT_DATA",
};
Build.platformTable["ti.platforms.evmDRA7XX:dsp2"] =
	Build.platformTable["ti.platforms.evmDRA7XX:dsp1"];



/*  Memory Map for ti.platforms.evmDRA7XX:ipu2
 *
 *  --- External Memory ---
 *  Virtual     Physical        Size            Comment
 *  ------------------------------------------------------------------------
 *  0000_4000   ????_????    5F_C000  (  ~6 MB) EXT_CODE
 *  8000_0000   ????_????    60_0000  (   6 MB) EXT_DATA
 *  8060_0000   ????_????   960_0000  (  86 MB) EXT_HEAP
 *  9F00_0000   9F00_0000     6_0000  ( 384 kB) TRACE_BUF
 *  9F06_0000   9F06_0000     1_0000  (  64 kB) EXC_DATA
 *  9F07_0000   9F07_0000     2_0000  ( 128 kB) PM_DATA (Power mgmt)
 */
var evmDRA7XX_ExtMemMapIpu2 = {
    EXT_CODE: {
        name: "EXT_CODE",
        base: 0x00004000,
        len:  0x005FC000,
        space: "code",
        access: "RWX"
    },
    EXT_DATA: {
        name: "EXT_DATA",
        base: 0x80000000,
        len:  0x00600000,
        space: "data",
        access: "RW"
    },
    EXT_HEAP: {
        name: "EXT_HEAP",
        base: 0x80600000,
        len:  0x09600000,
        space: "data",
        access: "RW"
    },
    TRACE_BUF: {
        name: "TRACE_BUF",
        base: 0x9F000000,
        len:  0x00060000,
        space: "data",
        access: "RW"
    },
    EXC_DATA: {
        name: "EXC_DATA",
        base: 0x9F060000,
        len:  0x00010000,
        space: "data",
        access: "RW"
    },
    PM_DATA: {
        name: "PM_DATA",
        base: 0x9F070000,
        len:  0x00020000,
        space: "data",
        access: "RWX"  /* should this have execute perm? */
    }
};

Build.platformTable["ti.platforms.evmDRA7XX:ipu2"] = {
    externalMemoryMap: [
        [ "EXT_CODE", evmDRA7XX_ExtMemMapIpu2.EXT_CODE ],
        [ "EXT_DATA", evmDRA7XX_ExtMemMapIpu2.EXT_DATA ],
        [ "EXT_HEAP", evmDRA7XX_ExtMemMapIpu2.EXT_HEAP ],
        [ "TRACE_BUF", evmDRA7XX_ExtMemMapIpu2.TRACE_BUF ],
        [ "EXC_DATA", evmDRA7XX_ExtMemMapIpu2.EXC_DATA ],
        [ "PM_DATA", evmDRA7XX_ExtMemMapIpu2.PM_DATA ]
    ],
    codeMemory: "EXT_CODE",
    dataMemory: "EXT_DATA",
    stackMemory: "EXT_DATA",
};

/*  Memory Map for ti.platforms.evmDRA7XX:ipu1
 *
 *  --- External Memory ---
 *  Virtual     Physical        Size            Comment
 *  ------------------------------------------------------------------------
 *  0000_4000   ????_????     F_C000  (  ~1 MB) EXT_CODE
 *  8000_0000   ????_????    20_0000  (   2 MB) EXT_DATA
 *  8020_0000   ????_????    30_0000  (   3 MB) EXT_HEAP
 *  9F00_0000   9F00_0000     6_0000  ( 384 kB) TRACE_BUF
 *  9F06_0000   9F06_0000     1_0000  (  64 kB) EXC_DATA
 *  9F07_0000   9F07_0000     2_0000  ( 128 kB) PM_DATA (Power mgmt)
 */
var evmDRA7XX_ExtMemMapIpu1 = {
    EXT_CODE: {
        name: "EXT_CODE",
        base: 0x00004000,
        len:  0x000FC000,
        space: "code",
        access: "RWX"
    },
    EXT_DATA: {
        name: "EXT_DATA",
        base: 0x80000000,
        len:  0x00200000,
        space: "data",
        access: "RW"
    },
    EXT_HEAP: {
        name: "EXT_HEAP",
        base: 0x80200000,
        len:  0x00300000,
        space: "data",
        access: "RW"
    },
    TRACE_BUF: {
        name: "TRACE_BUF",
        base: 0x9F000000,
        len:  0x00060000,
        space: "data",
        access: "RW"
    },
    EXC_DATA: {
        name: "EXC_DATA",
        base: 0x9F060000,
        len:  0x00010000,
        space: "data",
        access: "RW"
    },
    PM_DATA: {
        name: "PM_DATA",
        base: 0x9F070000,
        len:  0x00020000,
        space: "data",
        access: "RWX"  /* should this have execute perm? */
    }
};

Build.platformTable["ti.platforms.evmDRA7XX:ipu1"] = {
    externalMemoryMap: [
        [ "EXT_CODE", evmDRA7XX_ExtMemMapIpu1.EXT_CODE ],
        [ "EXT_DATA", evmDRA7XX_ExtMemMapIpu1.EXT_DATA ],
        [ "EXT_HEAP", evmDRA7XX_ExtMemMapIpu1.EXT_HEAP ],
        [ "TRACE_BUF", evmDRA7XX_ExtMemMapIpu1.TRACE_BUF ],
        [ "EXC_DATA", evmDRA7XX_ExtMemMapIpu1.EXC_DATA ],
        [ "PM_DATA", evmDRA7XX_ExtMemMapIpu1.PM_DATA ]
    ],
    codeMemory: "EXT_CODE",
    dataMemory: "EXT_DATA",
    stackMemory: "EXT_DATA",
};

    rsc_table_vayu_dsp.c file

    Fullscreen rsc_table_vayu_dsp.c.txt Download 
    /*
 * Copyright (c) 2012-2014, Texas Instruments Incorporated
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * *  Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 *
 * *  Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 *
 * *  Neither the name of Texas Instruments Incorporated nor the names of
 *    its contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */

/*
 *  ======== rsc_table_vayu_dsp.h ========
 *
 *  Define the resource table entries for all DSP cores. This will be
 *  incorporated into corresponding base images, and used by the remoteproc
 *  on the host-side to allocated/reserve resources.
 *
 */

#ifndef _RSC_TABLE_VAYU_DSP_H_
#define _RSC_TABLE_VAYU_DSP_H_

#include "rsc_types.h"

/* DSP Memory Map */
#define L4_DRA7XX_BASE          0x4A000000

#define L4_PERIPHERAL_L4CFG     (L4_DRA7XX_BASE)
#define DSP_PERIPHERAL_L4CFG    0x4A000000

#define L4_PERIPHERAL_L4PER1    0x48000000
#define DSP_PERIPHERAL_L4PER1   0x48000000

#define L4_PERIPHERAL_L4PER2    0x48400000
#define DSP_PERIPHERAL_L4PER2   0x48400000

#define L4_PERIPHERAL_L4PER3    0x48800000
#define DSP_PERIPHERAL_L4PER3   0x48800000

#define L4_PERIPHERAL_L4EMU     0x54000000
#define DSP_PERIPHERAL_L4EMU    0x54000000

#define L3_PERIPHERAL_DMM       0x4E000000
#define DSP_PERIPHERAL_DMM      0x4E000000

#define L3_TILER_MODE_0_1       0x60000000
#define DSP_TILER_MODE_0_1      0x60000000

#define L3_TILER_MODE_2         0x70000000
#define DSP_TILER_MODE_2        0x70000000

#define L3_TILER_MODE_3         0x78000000
#define DSP_TILER_MODE_3        0x78000000

#define DSP_MEM_TEXT            0x95000000
/* Co-locate alongside TILER region for easier flushing */
#define DSP_MEM_IOBUFS          0x80000000
#define DSP_MEM_DATA            0x95100000
#define DSP_MEM_HEAP            0x95600000

#define DSP_MEM_IPC_DATA        0x9F000000
#define DSP_MEM_IPC_VRING       0x99000000
#define DSP_MEM_RPMSG_VRING0    0x99000000
#define DSP_MEM_RPMSG_VRING1    0x99004000
#define DSP_MEM_VRING_BUFS0     0x99040000
#define DSP_MEM_VRING_BUFS1     0x99080000

#define DSP_PERIPHERAL_EDMA     0x43300000
#define L3_PERIPHERAL_EDMA      0x43300000
#define DSP_MCASP1_DATA         0x45800000
#define L3_MCASP1_DATA          0x45800000

#define DSP_MCASP2_DATA         0x45c00000
#define L3_MCASP2_DATA          0x45c00000

#define DSP_DDR_DATA            0x9B000000
#define L3_DDR_DATA             0x9B000000

#define DSP_MEM_IPC_VRING_SIZE  SZ_1M
#define DSP_MEM_IPC_DATA_SIZE   SZ_1M
#define DSP_MEM_TEXT_SIZE       SZ_1M
#define DSP_MEM_DATA_SIZE       (SZ_1M * 5)
#define DSP_MEM_HEAP_SIZE       (SZ_1M * 3)
#define DSP_MEM_IOBUFS_SIZE     (SZ_1M * 90)


/* NOTE: Make sure this matches what is configured in the linux device tree */
#define DSP_CMEM_IOBUFS 0xA0000000
#define PHYS_CMEM_IOBUFS 0xA0000000
#define DSP_CMEM_IOBUFS_SIZE (SZ_1M * 192)
/*
 * Assign fixed RAM addresses to facilitate a fixed MMU table.
 */

//BWC
#define VAYU_DSP_1

/* See CMA BASE addresses in Linux side: arch/arm/mach-omap2/remoteproc.c */
#if defined (VAYU_DSP_1)
#define PHYS_MEM_IPC_VRING      0x99000000
#elif defined (VAYU_DSP_2)
#define PHYS_MEM_IPC_VRING      0x9F000000
#endif

/* Need to be identical to that of IPU */
#define PHYS_MEM_IOBUFS         0xBA300000

/*
 * Sizes of the virtqueues (expressed in number of buffers supported,
 * and must be power of 2)
 */
#define DSP_RPMSG_VQ0_SIZE      256
#define DSP_RPMSG_VQ1_SIZE      256

/* flip up bits whose indices represent features we support */
#define RPMSG_DSP_C0_FEATURES         1

struct my_resource_table {
    struct resource_table base;

    UInt32 offset[21];  /* Should match 'num' in actual definition */

    /* rpmsg vdev entry */
    struct fw_rsc_vdev rpmsg_vdev;
    struct fw_rsc_vdev_vring rpmsg_vring0;
    struct fw_rsc_vdev_vring rpmsg_vring1;

    /* text carveout entry */
    struct fw_rsc_carveout text_cout;

    /* data carveout entry */
    struct fw_rsc_carveout data_cout;

    /* heap carveout entry */
    struct fw_rsc_carveout heap_cout;

    /* ipcdata carveout entry */
    struct fw_rsc_carveout ipcdata_cout;

    /* trace entry */
    struct fw_rsc_trace trace;

    /* devmem entry */
    struct fw_rsc_devmem devmem0;

    /* devmem entry */
    struct fw_rsc_devmem devmem1;

    /* devmem entry */
    struct fw_rsc_devmem devmem2;

    /* devmem entry */
    struct fw_rsc_devmem devmem3;

    /* devmem entry */
    struct fw_rsc_devmem devmem4;

    /* devmem entry */
    struct fw_rsc_devmem devmem5;

    /* devmem entry */
    struct fw_rsc_devmem devmem6;

    /* devmem entry */
    struct fw_rsc_devmem devmem7;

    /* devmem entry */
    struct fw_rsc_devmem devmem8;

    /* devmem entry */
    struct fw_rsc_devmem devmem9;

    /* devmem entry */
    struct fw_rsc_devmem devmem10;
    /* devmem entry */
    struct fw_rsc_devmem devmem11;

    /* devmem entry */
    struct fw_rsc_devmem devmem12;
    /* devmem entry */
        struct fw_rsc_devmem devmem13;
        /* devmem entry */
            struct fw_rsc_devmem devmem14;
};

//BWC added extern declaration
extern char ti_trace_SysMin_Module_State_0_outbuf__A;
#define TRACEBUFADDR (UInt32)&ti_trace_SysMin_Module_State_0_outbuf__A

#pragma DATA_SECTION(ti_ipc_remoteproc_ResourceTable, ".resource_table")
#pragma DATA_ALIGN(ti_ipc_remoteproc_ResourceTable, 4096)

struct my_resource_table ti_ipc_remoteproc_ResourceTable = {
    1,      /* we're the first version that implements this */
    21,     /* number of entries in the table */
    0, 0,   /* reserved, must be zero */
    /* offsets to entries */
    {
        offsetof(struct my_resource_table, rpmsg_vdev),
        offsetof(struct my_resource_table, text_cout),
        offsetof(struct my_resource_table, data_cout),
        offsetof(struct my_resource_table, heap_cout),
        offsetof(struct my_resource_table, ipcdata_cout),
        offsetof(struct my_resource_table, trace),
        offsetof(struct my_resource_table, devmem0),
        offsetof(struct my_resource_table, devmem1),
        offsetof(struct my_resource_table, devmem2),
        offsetof(struct my_resource_table, devmem3),
        offsetof(struct my_resource_table, devmem4),
        offsetof(struct my_resource_table, devmem5),
        offsetof(struct my_resource_table, devmem6),
        offsetof(struct my_resource_table, devmem7),
        offsetof(struct my_resource_table, devmem8),
        offsetof(struct my_resource_table, devmem9),
        offsetof(struct my_resource_table, devmem10),
        offsetof(struct my_resource_table, devmem11),
        offsetof(struct my_resource_table, devmem12),
        offsetof(struct my_resource_table, devmem13),
        offsetof(struct my_resource_table, devmem14),
    },

    /* rpmsg vdev entry */
    {
        TYPE_VDEV, VIRTIO_ID_RPMSG, 0,
        RPMSG_DSP_C0_FEATURES, 0, 0, 0, 2, { 0, 0 },
        /* no config data */
    },
    /* the two vrings */
    { DSP_MEM_RPMSG_VRING0, 4096, DSP_RPMSG_VQ0_SIZE, 1, 0 },
    { DSP_MEM_RPMSG_VRING1, 4096, DSP_RPMSG_VQ1_SIZE, 2, 0 },

    {
        TYPE_CARVEOUT,
        DSP_MEM_TEXT, 0,
        DSP_MEM_TEXT_SIZE, 0, 0, "DSP_MEM_TEXT",
    },

    {
        TYPE_CARVEOUT,
        DSP_MEM_DATA, 0,
        DSP_MEM_DATA_SIZE, 0, 0, "DSP_MEM_DATA",
    },

    {
        TYPE_CARVEOUT,
        DSP_MEM_HEAP, 0,
        DSP_MEM_HEAP_SIZE, 0, 0, "DSP_MEM_HEAP",
    },

    {
        TYPE_CARVEOUT,
        DSP_MEM_IPC_DATA, 0,
        DSP_MEM_IPC_DATA_SIZE, 0, 0, "DSP_MEM_IPC_DATA",
    },

    {
        TYPE_TRACE, TRACEBUFADDR, 0x8000, 0, "trace:dsp",
    },

    {
        TYPE_DEVMEM,
       DSP_MEM_IPC_VRING, PHYS_MEM_IPC_VRING,
       DSP_MEM_IPC_VRING_SIZE, 0, 0, "DSP_MEM_IPC_VRING",
    },

    {
        TYPE_DEVMEM,
        DSP_MEM_IOBUFS, PHYS_MEM_IOBUFS,
        DSP_MEM_IOBUFS_SIZE, 0, 0, "DSP_MEM_IOBUFS",
    },

    {
        TYPE_DEVMEM,
        DSP_TILER_MODE_0_1, L3_TILER_MODE_0_1,
        SZ_256M, 0, 0, "DSP_TILER_MODE_0_1",
    },

    {
        TYPE_DEVMEM,
        DSP_TILER_MODE_2, L3_TILER_MODE_2,
        SZ_128M, 0, 0, "DSP_TILER_MODE_2",
    },

    {
        TYPE_DEVMEM,
        DSP_TILER_MODE_3, L3_TILER_MODE_3,
        SZ_128M, 0, 0, "DSP_TILER_MODE_3",
    },

    {
        TYPE_DEVMEM,
        DSP_PERIPHERAL_L4CFG, L4_PERIPHERAL_L4CFG,
        SZ_16M, 0, 0, "DSP_PERIPHERAL_L4CFG",
    },

    {
        TYPE_DEVMEM,
        DSP_PERIPHERAL_L4PER1, L4_PERIPHERAL_L4PER1,
        SZ_2M, 0, 0, "DSP_PERIPHERAL_L4PER1",
    },

    {
        TYPE_DEVMEM,
        DSP_PERIPHERAL_L4PER2, L4_PERIPHERAL_L4PER2,
        SZ_4M, 0, 0, "DSP_PERIPHERAL_L4PER2",
    },

    {
        TYPE_DEVMEM,
        DSP_PERIPHERAL_L4PER3, L4_PERIPHERAL_L4PER3,
        SZ_8M, 0, 0, "DSP_PERIPHERAL_L4PER3",
    },

    {
        TYPE_DEVMEM,
        DSP_PERIPHERAL_L4EMU, L4_PERIPHERAL_L4EMU,
        SZ_16M, 0, 0, "DSP_PERIPHERAL_L4EMU",
    },

    {
        TYPE_DEVMEM,
        DSP_PERIPHERAL_DMM, L3_PERIPHERAL_DMM,
        SZ_1M, 0, 0, "DSP_PERIPHERAL_DMM",
    },

    {
        TYPE_DEVMEM,
        DSP_PERIPHERAL_EDMA, L3_PERIPHERAL_EDMA,
        SZ_1M*3, 0, 0, "DSP_PERIPHERAL_EDMA",
    },
    {
        TYPE_DEVMEM,
        DSP_DDR_DATA, L3_DDR_DATA,
        SZ_1M, 0, 0, "DSP_DDR_DATA",
    },

    {
        TYPE_DEVMEM,
        DSP_CMEM_IOBUFS, PHYS_CMEM_IOBUFS,
        DSP_CMEM_IOBUFS_SIZE, 0, 0, "DSP_CMEM_IOBUFS",
    },

    {
         TYPE_DEVMEM,
         DSP_MCASP2_DATA, L3_MCASP2_DATA,
         SZ_1M*8, 0, 0, "DSP_MCASP2_DATA",
    },
};

#endif /* _RSC_TABLE_VAYU_DSP_H_ */

     

     

    warning

    [  231.251045] remoteproc remoteproc1: crash detected in 55020000.ipu: type watchdog
[  231.258614] remoteproc remoteproc1: crash detected in 55020000.ipu: type watchdog
[  231.266207] remoteproc remoteproc1: handling crash #2 in 55020000.ipu
[  231.276428] remoteproc remoteproc1: recovering 55020000.ipu
[  231.313491] remoteproc remoteproc1: stopped remote processor 55020000.ipu
[  231.320331] remoteproc remoteproc1: powering up 55020000.ipu
[  231.376282] remoteproc remoteproc1: Booting fw image dra7-ipu2-fw.xem4, size 3743164
[  231.401152] omap-iommu 55082000.mmu: 55082000.mmu: version 2.1
[  231.555598] omap-iommu 55082000.mmu: iommu fault: da 0x0 flags 0x0
[  231.561822] remoteproc remoteproc1: crash detected in 55020000.ipu: type mmufault
[  231.569344] omap-iommu 55082000.mmu: 55082000.mmu: errs:0x00000002 da:0x00000000 pgd:0xdfb74000 *pgd:px95100002
[  231.613305] virtio_rpmsg_bus virtio2: rpmsg host is online
[  231.618846] remoteproc remoteproc1: registered virtio2 (type 7)
[  231.642179] remoteproc remoteproc1: remote processor 55020000.ipu is now up
[  231.683745] prueth pruss1_eth: port 1: using random MAC addr: 1e:e5:39:ea:47:aa

    cat /proc/iomem & dmesg | grep -i cma

    

    root@am57xx-evm:/lib/firmware# cat /proc/iomem              
40300000-4037ffff : 40300000.ocmcram
40800000-40847fff : l2ram
40d01000-40d010ff : /ocp/mmu@40d01000
40d02000-40d020ff : /ocp/mmu@40d02000
43300000-433fffff : edma3_cc
44000000-44ffffff : /ocp
45000000-45000fff : /ocp
48020000-4802001f : serial
48032000-4803207f : /ocp/timer@48032000
48034000-4803407f : /ocp/timer@48034000
48036000-4803607f : /ocp/timer@48036000
4803e000-4803e07f : /ocp/timer@4803e000
48051000-480511ff : /ocp/gpio@48051000
48053000-480531ff : /ocp/gpio@48053000
48055000-480551ff : /ocp/gpio@48055000
48057000-480571ff : /ocp/gpio@48057000
48059000-480591ff : /ocp/gpio@48059000
4805b000-4805b1ff : /ocp/gpio@4805b000
4805d000-4805d1ff : /ocp/gpio@4805d000
48060000-480600ff : /ocp/i2c@48060000
48070000-480700ff : /ocp/i2c@48070000
4807a000-4807a0ff : /ocp/i2c@4807a000
48086000-4808607f : /ocp/timer@48086000
48088000-4808807f : /ocp/timer@48088000
48090000-48091fff : /ocp/rng@48090000
48098100-480982ff : /ocp/spi@48098000
4809a100-4809a2ff : /ocp/spi@4809a000
4809c000-4809c3ff : /ocp/mmc@4809c000
480a5000-480a509f : /ocp/des@480a5000
480ad000-480ad3ff : /ocp/mmc@480ad000
480b4000-480b43ff : /ocp/mmc@480b4000
480d1000-480d13ff : /ocp/mmc@480d1000
48440200-4844027f : /ocp/epwmss@48440000/pwm@48440200
4844a000-4844ad1b : /ocp/padconf@4844a000
48484000-48484fff : /ocp/ethernet@48484000
48485000-484850ff : /ocp/ethernet@48484000/mdio@48485000
48485200-48487fff : /ocp/ethernet@48484000
48820000-4882007f : /ocp/timer@48820000
48822000-4882207f : /ocp/timer@48822000
48824000-4882407f : /ocp/timer@48824000
48826000-4882607f : /ocp/timer@48826000
48828000-4882807f : /ocp/timer@48828000
4882a000-4882a07f : /ocp/timer@4882a000
4882c000-4882c07f : /ocp/timer@4882c000
4882e000-4882e07f : /ocp/timer@4882e000
4883c000-4883c1ff : /ocp/mailbox@4883c000
4883e000-4883e1ff : /ocp/mailbox@4883e000
48840000-488401ff : /ocp/mailbox@48840000
48842000-488421ff : /ocp/mailbox@48842000
48880000-4888ffff : /ocp/omap_dwc3_1@48880000
48890000-48897fff : /ocp/omap_dwc3_1@48880000/usb@48890000
  48890000-48897fff : /ocp/omap_dwc3_1@48880000/usb@48890000
4889c100-488a6fff : /ocp/omap_dwc3_1@48880000/usb@48890000
488c0000-488cffff : /ocp/omap_dwc3_2@488c0000
488d0000-488d7fff : /ocp/omap_dwc3_2@488c0000/usb@488d0000
  488d0000-488d7fff : /ocp/omap_dwc3_2@488c0000/usb@488d0000
488dc100-488e6fff : /ocp/omap_dwc3_2@488c0000/usb@488d0000
48970000-48970113 : vip
48975500-489755d7 : parser0
48975700-48975717 : csc0
48975800-4897587f : sc0
48975a00-48975ad7 : parser1
48975c00-48975c17 : csc1
48975d00-48975d7f : sc1
489d0700-489d077f : sc
489d5700-489d5717 : csc
4a0021e0-4a0021eb : /ocp/bandgap@4a0021e0
4a00232c-4a002337 : /ocp/bandgap@4a0021e0
4a002380-4a0023ab : /ocp/bandgap@4a0021e0
4a0023c0-4a0023fb : /ocp/bandgap@4a0021e0
4a00246c-4a00246f : ldo-address
4a002470-4a002473 : ldo-address
4a002554-4a002557 : gmii-sel
4a002564-4a00256b : /ocp/bandgap@4a0021e0
4a002574-4a0025c3 : /ocp/bandgap@4a0021e0
4a002b78-4a002c73 : /ocp/l4@4a000000/scm@2000/dma-router@b78
4a002c78-4a002cf3 : /ocp/l4@4a000000/scm@2000/dma-router@c78
4a002e8c-4a002e8f : pinctrl-single
4a003400-4a003867 : pinctrl-single
4a056000-4a056fff : omap_dma_system.0
  4a056000-4a056fff : /ocp/dma-controller@4a056000
4a080000-4a08001f : /ocp/ocp2scp@4a080000
4a084000-4a0843ff : /ocp/ocp2scp@4a080000/phy@4a084000
4a084c00-4a084c3f : pll_ctrl
4a085000-4a0853ff : /ocp/ocp2scp@4a080000/phy@4a085000
4a090000-4a09001f : /ocp/ocp2scp@4a090000
4a096800-4a09683f : pll_ctrl
4ae07ddc-4ae07ddf : setup-address
4ae07de0-4ae07de3 : control-address
4ae07de4-4ae07de7 : setup-address
4ae07de8-4ae07deb : control-address
4ae07e20-4ae07e23 : control-address
4ae07e24-4ae07e27 : control-address
4ae07e30-4ae07e33 : setup-address
4ae07e34-4ae07e37 : setup-address
4ae0c154-4ae0c157 : ldo-address
4ae0c158-4ae0c15b : ldo-address
4ae10000-4ae101ff : /ocp/gpio@4ae10000
4ae14000-4ae1407f : /ocp/wdt@4ae14000
4ae20000-4ae2007f : /ocp/timer@4ae20000
4b101000-4b1012ff : /ocp/sham@53100000
4b200000-4b201fff : dram0
4b202000-4b203fff : dram1
4b210000-4b217fff : shrdram2
4b220000-4b221fff : intc
4b222000-4b2223ff : control
4b222400-4b2224ff : debug
4b224000-4b2243ff : control
4b224400-4b2244ff : debug
4b226000-4b227fff : cfg
4b22e000-4b22e31b : iep
4b232000-4b232057 : mii_rt
4b234000-4b236fff : iram
4b238000-4b23afff : iram
4b280000-4b281fff : dram0
4b282000-4b283fff : dram1
4b290000-4b297fff : shrdram2
4b2a0000-4b2a1fff : intc
4b2a2000-4b2a23ff : control
4b2a2400-4b2a24ff : debug
4b2a4000-4b2a43ff : control
4b2a4400-4b2a44ff : debug
4b2a6000-4b2a7fff : cfg
4b2ae000-4b2ae31b : iep
4b2b2000-4b2b2057 : mii_rt
4b2b4000-4b2b6fff : iram
4b2b8000-4b2bafff : iram
4b300000-4b3000ff : qspi_base
4b500000-4b50009f : /ocp/aes@4b500000
4b700000-4b70009f : /ocp/aes@4b700000
55020000-5502ffff : l2ram
55082000-550820ff : /ocp/mmu@55082000
58004054-58004057 : pll1_clkctrl
58004300-5800431f : pll1
58040000-580401ff : wp
58040200-5804027f : pll
58040300-5804037f : phy
58060000-58078fff : core
58820000-5882ffff : l2ram
58882000-588820ff : /ocp/mmu@58882000
80000000-9fffffff : System RAM
  80008000-80dfffff : Kernel code
  81000000-8109b1ef : Kernel data
a0000000-abffffff : CMEM
ac000000-bfdfffff : System RAM
root@am57xx-evm:/lib/firmware# dmesg | grep -i cma          
[    0.000000] Reserved memory: created CMA memory pool at 0x0000000095000000, size 64 MiB
[    0.000000] OF: reserved mem: initialized node ipu2_cma@95000000, compatible id shared-dma-pool
[    0.000000] Reserved memory: created CMA memory pool at 0x0000000099000000, size 64 MiB
[    0.000000] OF: reserved mem: initialized node dsp1_cma@99000000, compatible id shared-dma-pool
[    0.000000] Reserved memory: created CMA memory pool at 0x000000009d000000, size 32 MiB
[    0.000000] OF: reserved mem: initialized node ipu1_cma@9d000000, compatible id shared-dma-pool
[    0.000000] cma: Reserved 24 MiB at 0x00000000be400000
[    0.000000] Memory: 637368K/849920K available (8192K kernel code, 317K rwdata, 2472K rodata, 2048K init, 296K bss, 24136K reserved, 188416K cma-reserved, 235520K highmem)
[    7.793251] omap-rproc 58820000.ipu: assigned reserved memory node ipu1_cma@9d000000
[    7.942490] omap-rproc 55020000.ipu: assigned reserved memory node ipu2_cma@95000000
[    8.101474] omap-rproc 40800000.dsp: assigned reserved memory node dsp1_cma@99000000
    

    

    

    regards
    

    June
    
			
    

		
		
		
		
	
    
	
    
		
    
			
		
    
	
    

	            
                	
	
    
				
		                
                
                
                
                
                
                
        		
		
				
    
			
		
    
		
		 
		
		
     
    
	
    

    
			
    
			
    
		
    

		
    
	
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													0
							
			
				
									
							
						
				
			
			
			
												
						in reply to jian35385
					
									
    
	
    
	                                    
                      
    
                        
                          Prodigy
                        150 points
                      
    
                          
                   		
		
    
					
    Jian,
    

    I just modified the .dts file, and tested again.
    

    

    .dts file
    

    ipu2_cma@95000000 {
	compatible = "shared-dma-pool";
	reg = <0x0 0x95000000 0x0 0x4000000>;
	reusable;
	status = "okay";
	linux,phandle = <0xbd>;
	phandle = <0xbd>;
};
    

    



    
    
    
        Fullscreen
        1614.am570x-mid.dts.txt
        Download
    
    
    
    /*
 * Copyright (C) 2015-2016 Texas Instruments Incorporated - http://www.ti.com/
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */
/dts-v1/;

#include "dra72x.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/clk/ti-dra7-atl.h>
#include "am57xx-idk-common.dtsi"

/ {
	model = "TI AM5718 IDK";
	compatible = "ti,am5718-idk", "ti,am5718", "ti,dra7";

	chosen {
		 bootargs = "console=ttyO2,115200n8 root=/dev/mmcblk0p2 rw rootfstype=ext4 rootwait lpj=61475";
		 //bootargs = "console=ttyO2,115200n8 root=/dev/mmcblk1p2 rw rootfstype=ext4 rootwait";
	};
	aliases {
		ethernet4 = &pruss1_emac0;
		ethernet5 = &pruss1_emac1;
        /delete-property/ rtc1;
        rtc0 = &rv3028; 
                //sound0 = &sound0;
                sound1 = &hdmi;
		/delete-property/ ethernet2;
		/delete-property/ ethernet3;
		/delete-property/ ethernet4;
		/delete-property/ ethernet5;
		display0 = &lcd;
		display1 = &hdmi0;
	};

    /delete-node/ pruss1_eth;
    /delete-node/ pruss2_eth;
    /delete-node/ leds-iio;
    /delete-node/ encoder@0;

    lcd_bl: backlight {
        compatible = "pwm-backlight";
        pwms = <&ehrpwm1 0 50000 0>;
        //pwms = <&ecap0 0 50000 1>;
        brightness-levels = <1 25 50 75 128 158 175 200 220 254>;
        default-brightness-level = <4>;
        //enable-gpios = <&gpio5 6 GPIO_ACTIVE_HIGH>;
    };

    lcd: display {
         compatible = "panel-dpi";

         label = "lcd";

         enable-gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>;

         backlight = <&lcd_bl>;

         /*panel-timing {
             clock-frequency = <51000000>;
             hactive = <1024>;
             vactive = <600>;
             hfront-porch = <290>;
             hback-porch = <20>;
             hsync-len = <10>;
             vback-porch = <20>;
             vfront-porch = <10>;
             vsync-len = <5>;
             hsync-active = <0>;
             vsync-active = <0>;
             de-active = <1>;
             pixelclk-active = <0>;
         };*/
	panel-timing {
		clock-frequency = <65000000>;
		hactive = <1280>;
		vactive = <800>;
		hfront-porch = <24>;
		hback-porch = <24>;
		hsync-len = <2>;
		vfront-porch = <5>;
		vback-porch = <5>;
		vsync-len = <2>;
		hsync-active = <0>;
		vsync-active = <0>;
		de-active = <1>;
		pixelclk-active = <0>;
	};

         port {
            lcd_in: endpoint {
            remote-endpoint = <&dpi_out>;
            };
         };
     };

	memory@80000000 {
		device_type = "memory";
		reg = <0x0 0x80000000 0x0 0x40000000>;
	};

    ocp{
        /delete-node/ sata@4a141100;
        /delete-node/ rtc@48838000;
        /delete-node/ omap_dwc3_3@48900000;
    };

	evm_12v0: fixedregulator-evm12v0 {
		/* main supply */
		compatible = "regulator-fixed";
		regulator-name = "evm_12v0";
		regulator-min-microvolt = <12000000>;
		regulator-max-microvolt = <12000000>;
		regulator-always-on;
		regulator-boot-on;
		/*gpio = <&gpio6 13 0>;
		enable-active-high;*/
	};

	evm_5v0: fixedregulator-evm5v0 {
		/* Output 1 of TPS43351QDAPRQ1 on dra72-evm */
		/* Output 1 of LM5140QRWGTQ1 on dra71-evm */
		compatible = "regulator-fixed";
		regulator-name = "evm_5v0";
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
		vin-supply = <&evm_12v0>;
		regulator-always-on;
		regulator-boot-on;
	};

	vsys_3v3: fixedregulator-vsys3v3 {
		/* Output 2 of TPS43351QDAPRQ1 on dra72-evm */
		/* Output 2 of LM5140QRWGTQ1 on dra71-evm */
		compatible = "regulator-fixed";
		regulator-name = "vsys_3v3";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		vin-supply = <&evm_12v0>;
		regulator-always-on;
		regulator-boot-on;
	};

	emmcex_3v3: fixedregulator-emmcex3v3 {
		compatible = "regulator-fixed";
		regulator-name = "emmcex_3v3";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		vin-supply = <&evm_12v0>;
		gpio = <&gpio4 5 0>;
		startup-delay-us = <2000>;
		enable-active-high;
	};

	emmcex_oe: fixedregulator-emmcexoe {
		compatible = "regulator-fixed";
		regulator-name = "emmcex_oe";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		vin-supply = <&emmcex_3v3>;
		gpio = <&gpio1 14 0>;
		startup-delay-us = <2000>;
		enable-active-low;
	};

	vsys_1v8: fixedregulator-vsys1v8 {
		/* Output 2 of TPS43351QDAPRQ1 on dra72-evm */
		/* Output 2 of LM5140QRWGTQ1 on dra71-evm */
		compatible = "regulator-fixed";
		regulator-name = "vsys_1v8";
		regulator-min-microvolt = <1800000>;
		regulator-max-microvolt = <1800000>;
		vin-supply = <&evm_12v0>;
		regulator-always-on;
		regulator-boot-on;
	};


	vmmcwl_fixed: fixedregulator-mmcwl {
		compatible = "regulator-fixed";
		regulator-name = "vmmcwl_fixed";
		regulator-min-microvolt = <1800000>;
		regulator-max-microvolt = <1800000>;
		gpio = <&gpio4 7 0>;
		startup-delay-us = <70000>;
		enable-active-high;
		vin-supply = <&evm_12v0>;
		//regulator-always-on;
		//regulator-boot-on;
	};


    extcon_usb1: extcon_usb1 {
        compatible = "linux,extcon-usb-gpio";
        //id-gpio = <&gpio2 24 GPIO_ACTIVE_HIGH>;
        vbus-gpio = <&gpio6 12 GPIO_ACTIVE_HIGH>;
     };

    extcon_usb2: extcon_usb2 {
        compatible = "linux,extcon-usb-gpio";
        id-gpio = <&gpio2 25 GPIO_ACTIVE_HIGH>;
        //vbus-gpio = <&gpio6 13 GPIO_ACTIVE_HIGH>;
     };

	reserved-memory {
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

        cmem_block_mem_0: cmem_block_mem@a0000000 {
          reg = <0x0 0xa0000000 0x0 0x0c000000>;
          no-map;
          status = "okay";
        };

		ipu2_cma_pool: ipu2_cma@95000000 {
			compatible = "shared-dma-pool";
			reg = <0x0 0x95000000 0x0 0x4000000>;
			reusable;
			status = "okay";
		};

		dsp1_cma_pool: dsp1_cma@99000000 {
			compatible = "shared-dma-pool";
			reg = <0x0 0x99000000 0x0 0x4000000>;
			reusable;
			status = "okay";
		};

		ipu1_cma_pool: ipu1_cma@9d000000 {
			compatible = "shared-dma-pool";
			reg = <0x0 0x9d000000 0x0 0x2000000>;
			reusable;
			status = "okay";
		};
	};

    cmem {
        compatible = "ti,cmem";
        #address-cells = <1>;
        #size-cells = <0>;

        #pool-size-cells = <2>;

        status = "okay";

        cmem_block_0: cmem_block@0 {
            reg = <0>;
            memory-region = <&cmem_block_mem_0>;
            cmem-buf-pools = <1 0x0 0x0c000000>;
        };
    };
    gpio-keys {
        compatible = "gpio-keys";
        autorepeat;

		set {
			label = "Key_set";
			linux,code = <103>;
			gpios = <&gpio4 3 GPIO_ACTIVE_LOW>;
		};

		ok {
			label = "Key_ok";
			linux,code = <104>;
			gpios = <&gpio4 4 GPIO_ACTIVE_LOW>;
		};
		emmc {
			label = "Key_emmc";
			linux,code = <105>;
			gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
		};
    };
	leds {
		compatible = "gpio-leds";
		/*wdt-led {
			label = "wdt";
			gpios = <&gpio6 11 GPIO_ACTIVE_LOW>;
			default-state = "on";
			linux,default-trigger = "heartbeat";
		};*/


		h41-led {
			label = "h41";
			gpios = <&gpio4 8 GPIO_ACTIVE_HIGH>;
			default-state = "off";
			linux,default-trigger = "none";
		};

		h42-led {
			label = "h42";
			gpios = <&gpio4 9 GPIO_ACTIVE_HIGH>;
			default-state = "off";
			linux,default-trigger = "none";
		};

		h43-led {
			label = "h43";
			gpios = <&gpio4 11 GPIO_ACTIVE_HIGH>;
			default-state = "off";
			linux,default-trigger = "none";
		};

		h44-led {
			label = "h44";
			gpios = <&gpio4 12 GPIO_ACTIVE_HIGH>;
			default-state = "off";
			linux,default-trigger = "none";
		};

		h51-led {
			label = "h51";
			gpios = <&gpio5 4 GPIO_ACTIVE_HIGH>;
			default-state = "on";
			linux,default-trigger = "none";
		};

		h52-led {
			label = "h52";
			gpios = <&gpio6 7 GPIO_ACTIVE_HIGH>;
			default-state = "on";
			linux,default-trigger = "heartbeat";
		};

		h53-led {
			label = "h53";
			gpios = <&gpio6 14 GPIO_ACTIVE_HIGH>;
			default-state = "off";
			linux,default-trigger = "mmc2";
		};

		h54-led {
			label = "h54";
			gpios = <&gpio6 15 GPIO_ACTIVE_HIGH>;
			default-state = "off";
			linux,default-trigger = "none";
		};

		h61-led {
			label = "h61";
			gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>;
			default-state = "off";
			linux,default-trigger = "none";
		};

		h62-led {
			label = "h62";
			gpios = <&gpio3 29 GPIO_ACTIVE_HIGH>;
			default-state = "off";
			linux,default-trigger = "none";
		};

		h63-led {
			label = "h63";
			gpios = <&gpio7 23 GPIO_ACTIVE_HIGH>;
			default-state = "off";
			linux,default-trigger = "none";
		};

		h64-led {
			label = "h64";
			gpios = <&gpio7 31 GPIO_ACTIVE_HIGH>;
			default-state = "off";
			linux,default-trigger = "none";
		};
	};

	/* Dual mac ethernet application node on icss2 */
	pruss1_eth: pruss1_eth {
		status = "okay";
		compatible = "ti,am57-prueth";
		pruss = <&pruss1>;
		sram = <&ocmcram1>;
		interrupt-parent = <&pruss1_intc>;

		pruss1_emac0: ethernet-mii0 {
			phy-handle = <&pruss1_eth0_phy>;
			phy-mode = "mii";
			interrupts = <20>, <22>;
			interrupt-names = "rx", "tx";
			/* Filled in by bootloader */
			local-mac-address = [00 00 00 00 00 00];
		};

		pruss1_emac1: ethernet-mii1 {
			phy-handle = <&pruss1_eth1_phy>;
			phy-mode = "mii";
			interrupts = <21>, <23>;
			interrupt-names = "rx", "tx";
			/* Filled in by bootloader */
			local-mac-address = [00 00 00 00 00 00];
		};
	};
	sound0: sound@0 {
		compatible = "simple-audio-card";
		simple-audio-card,name = "DRA7xx-EVM";
		simple-audio-card,format = "i2s";
		//simple-audio-card,mclk-fs = <128>;
		simple-audio-card,bitclock-master = <&sound_master>;
		simple-audio-card,frame-master = <&sound_master>;
		simple-audio-card,widgets =
			"Headphone", "Headphone Jack",
			"Line", "Line In";
		simple-audio-card,routing =
			"Headphone Jack",	"SPK_LP",
			"Headphone Jack",	"SPK_RP",
			"LINPUT1",		"Line In",
			"RINPUT1",		"Line In";

		dailink0_master: simple-audio-card,cpu {
			sound-dai = <&mcasp4>;
		};

		sound_master: simple-audio-card,codec {
			sound-dai = <&tlv320aic34_a>;
			system-clock-frequency = <12000000>;
		};
	};
};


&cpu0_opp_table {
       opp_500@500000000 {
               opp-hz = /bits/ 64 <500000000>;
               opp-microvolt = <1060000 850000 1150000>,
                       <1060000 850000 1150000>;
               opp-supported-hw = <0xFF 0x01>;
       };
       opp_200@200000000 {
               opp-hz = /bits/ 64 <200000000>;
               opp-microvolt = <1060000 850000 1150000>,
                       <1060000 850000 1150000>;
               opp-supported-hw = <0xFF 0x01>;
       };

        /delete-node/ opp_od@1176000000;
        /delete-node/ opp_high@1500000000;
      
};

&mac {
	status = "okay";
	//dual_emac;
};

&phy_sel {
	rmii-clock-ext;
};

&cpsw_emac0 {
	phy_id = <&davinci_mdio>, <3>;
};

&cpsw_emac1 {
	phy_id = <&davinci_mdio>, <0>;
};

&davinci_mdio {
	pinctrl-names = "default", "sleep";
	pinctrl-0 = <&davinci_mdio_pins_default>;
	pinctrl-1 = <&davinci_mdio_pins_sleep>;
};

&i2c1 {
	status = "okay";

	lp8733: lp8733@60 {
		compatible = "ti,lp8733";
		reg = <0x60>;

		buck0-in-supply =<&vsys_3v3>;
		buck1-in-supply =<&vsys_3v3>;
		ldo0-in-supply =<&evm_5v0>;
		ldo1-in-supply =<&evm_5v0>;

		lp8733_regulators: regulators {
			lp8733_buck0_reg: buck0 {
				/* FB_B0 -> LP8733-BUCK1 - VPO_S1_AVS - VDD_CORE_AVS (core, mpu, gpu) */
				regulator-name = "lp8733-buck0";
				regulator-min-microvolt = <850000>;
				regulator-max-microvolt = <1250000>;
				regulator-always-on;
				regulator-boot-on;
			};

			lp8733_buck1_reg: buck1 {
				/* FB_B1 -> LP8733-BUCK2 - VPO_S2_AVS - VDD_DSP_AVS (DSP/eve/iva) */
				regulator-name = "lp8733-buck1";
				regulator-min-microvolt = <850000>;
				regulator-max-microvolt = <1250000>;
				regulator-boot-on;
				regulator-always-on;
			};

			lp8733_ldo0_reg: ldo0 {
				/* LDO0 -> LP8733-LDO1 - VPO_L1_3V3 - VDDSHV8 (optional) */
				regulator-name = "lp8733-ldo0";
				regulator-min-microvolt = <3300000>;
				regulator-max-microvolt = <3300000>;
				regulator-boot-on;
				regulator-always-on;
			};

			lp8733_ldo1_reg: ldo1 {
				/* LDO1 -> LP8733-LDO2 - VPO_L2_3V3 - VDDA_USB3V3 */
				regulator-name = "lp8733-ldo1";
				regulator-min-microvolt = <3300000>;
				regulator-max-microvolt = <3300000>;
				regulator-always-on;
				regulator-boot-on;
			};
		};
	};

	lp8732: lp8732@61 {
		compatible = "ti,lp8732";
		reg = <0x61>;

		buck0-in-supply =<&vsys_3v3>;
		buck1-in-supply =<&vsys_3v3>;
		ldo0-in-supply =<&vsys_3v3>;
		ldo1-in-supply =<&vsys_3v3>;

		lp8732_regulators: regulators {
			lp8732_buck0_reg: buck0 {
				/* FB_B0 -> LP8732-BUCK1 - VPO_S3_1V8 - VDDS_1V8 */
				regulator-name = "lp8732-buck0";
				regulator-min-microvolt = <1800000>;
				regulator-max-microvolt = <1800000>;
				regulator-always-on;
				regulator-boot-on;
			};

			lp8732_buck1_reg: buck1 {
				/* FB_B1 -> LP8732-BUCK2 - VPO_S4_DDR - VDD_DDR_1V35 */
				regulator-name = "lp8732-buck1";
				regulator-min-microvolt = <1350000>;
				regulator-max-microvolt = <1350000>;
				regulator-boot-on;
				regulator-always-on;
			};

			lp8732_ldo0_reg: ldo0 {
				/* LDO0 -> LP8732-LDO1 - VPO_L3_1V8 - VDA_1V8_PLL */
				regulator-name = "lp8732-ldo0";
				regulator-min-microvolt = <1800000>;
				regulator-max-microvolt = <1800000>;
				regulator-boot-on;
				regulator-always-on;
			};

			lp8732_ldo1_reg: ldo1 {
				/* LDO1 -> LP8732-LDO2 - VPO_L4_1V8 - VDA_1V8_PHY */
				regulator-name = "lp8732-ldo1";
				regulator-min-microvolt = <1800000>;
				regulator-max-microvolt = <1800000>;
				regulator-always-on;
				regulator-boot-on;
			};
		};
	};

    	rtc_pcf8563: rtc@51 {
            compatible = "nxp,pcf8563";
            reg = <0x51>;
	    status = "disable";
            interrupt-parent = <&gpio6>;
            interrupts = <16 IRQ_TYPE_EDGE_FALLING>;
        };

        /delete-node/ tc358778@0e;
        /delete-node/ tpic2810@60;
    	tps659038@58 {
           /delete-node/ tps659038_usb;
        };
	ov2659@30 {
	    status = "disabled";
	};
        PCM1862: PCM1860@4a {

        compatible = "ti,pcm18xx";
             reg = <0x4a>;
        };
        PCM1863: PCM1861@4b {
        compatible = "ti,pcm18xx";
            reg = <0x4b>;
        };
        is31fl3236: led-controller@3c {
	        compatible = "issi,is31fl3236";
	        reg = <0x3c>;
	        #address-cells = <1>;
	        #size-cells = <0>;

	        led@1 {
		       reg = <1>;
		       label = "AngelLed";
               linux,default-trigger = "default-off";
	        };
        };

        lkt4106: lkt4106@28 {
        compatible = "lkt4106";
             reg = <0x28>;
        };

        rv3028: rv3028@52 {
		compatible = "microcrystal,rv3028";
		reg = <0x52>;
		interrupt-parent = <&gpio1>;
		interrupts = <0 IRQ_TYPE_EDGE_FALLING>;
        };
};


&i2c3 {
	pinctrl-names = "default";
	pinctrl-0 = <&i2c3_pins_default>;

	clock-frequency = <400000>;
	status = "okay";
	wm8960: wm8960@1a {
		#sound-dai-cells = <0>;
        compatible = "wlf,wm8960";
        reg = <0x1a>;
        wlf,shared-lrclk;

       };
	eeprom_core: eeprom_core@50 {
        compatible = "atmel,24c256";
        reg = <0x50>;
        pagesize = <32>;
        status = "okay";
		     };

};

/*
&i2c4 {
	status = "okay";
	clock-frequency = <400000>;

	pinctrl-names = "default";
	pinctrl-0 = <&i2c4_pins_default>;

        PCM1860: PCM1860@4a {

        compatible = "ti,pcm18xx";
           reg = <0x4a>;
        };
        PCM1861: PCM1861@4b {
        compatible = "ti,pcm18xx";
        reg = <0x4b>;
        };
        AIC31: AIC31@1b {
         compatible = "ti,AIC31XX";
               reg = <0x1b>;
        };
        AIC31_2: AIC31@18 {
         compatible = "ti,AIC31XX";
               reg = <0x18>;
        };

};
*/
&i2c4 {
	status = "okay";
	clock-frequency = <400000>;

	pinctrl-names = "default";
	pinctrl-0 = <&i2c4_pins_default>;

	 tlv320aic34_a: tlv320aic34_a@1a {
                #sound-dai-cells = <0>;
                compatible = "ti,tlv320aic3x";
                reg = <0x1a>;
                adc-settle-ms = <40>;
                ai3x-micbias-vg = <1>;
                status = "disabled";

                AVDD-supply = <&vsys_3v3>;
                IOVDD-supply = <&vsys_3v3>;
                DRVDD-supply = <&vsys_3v3>;
		DVDD-supply = <&vsys_1v8>;
        };
	aic34_1@1a {
        compatible = "ti,aic3x";
        reg  = <0x1a>;
  
    };
    aic34_2@1b {
        compatible = "ti,aic3x";
        reg = <0x1b>;
    };
  
  
    mcp4441@2d {
	status = "disabled";
    	compatible = "microchip,mcp4441-103";
        reg = <0x2d>;
        gpio-addr-a0 = <&gpio2 29 GPIO_ACTIVE_LOW>;
    };

    ds1881_1@28 {
    	compatible = "maxim,ds1881-045";
        reg = <0x28>;
        enable-gpios = <&gpio2 29 GPIO_ACTIVE_LOW>;
    };

    /* PCM1860: PCM1860@4a {

        compatible = "ti,pcm18xx";
           reg = <0x4a>;
     };
        PCM1861: PCM1861@4b {
        compatible = "ti,pcm18xx";
        reg = <0x4b>;
        };
        AIC31: AIC31@1b {
         compatible = "ti,AIC31XX";
               reg = <0x1b>;
        };
        AIC31_2: AIC31@18 {
         compatible = "ti,AIC31XX";
               reg = <0x18>;
        };
     */
	/*hy461x@38 {
		compatible = "qcom,hy461x";
		reg = <0x38>;
		//pinctrl-names = "default";
		//pinctrl-0 = <&tp_pin>;

		qcom,ts-gpio-reset = <&gpio2 2 GPIO_ACTIVE_HIGH>;
		qcom,ts-gpio-irq = <&gpio2 27 GPIO_ACTIVE_HIGH>;

		qcom,max-x = <1024>;
		qcom,max-y = <600>;
		qcom,hard-reset-delay-ms = <220>;
		qcom,soft-reset-delay-ms = <220>;
	};

	goodix_ts@5d {
		compatible = "goodix,gt9xx";
		reg = <0x5d>;
		goodix,irq-gpio = <&gpio2 27 IRQ_TYPE_EDGE_RISING>;
		goodix,rst-gpio = <&gpio2 2 GPIO_ACTIVE_LOW>;
		goodix,cfg-group2 = [
00 00 05 20 03 05 0D 00 01 C8 28 0F 50 32 03 05 00 00 00 00 00 00 00 00 00 00 00 90 30 AA 20 1E 0C 08 00 00 00 9A 02 2D 00 00 00 00 00 00 00 00 00 00 00 0F 2D 94 C5 02 07 00 00 04 E0 10 00 B8 14 00 92 1A 00 7A 20 00 65 28 00 64 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 19 18 17 16 15 14 11 10 0F 0E 0D 0C 09 08 07 06 05 04 01 00 00 00 00 00 00 00 00 00 00 00 2A 29 28 27 26 25 24 23 22 21 20 1F 1E 1C 1B 19 14 13 12 11 10 0F 0E 0D 0C 0A 08 07 06 04 02 00 00 00 00 00 00 00 00 00 00 00 43 01
		];
	};

	tlv320aic3106: tlv320aic3106@1b {
		#sound-dai-cells = <0>;
		compatible = "ti,tlv320aic3106";
		reg = <0x1b>;
		adc-settle-ms = <40>;
		ai3x-micbias-vg = <1>;
		assigned-clocks = <&clkoutmux2_clk_mux>;
		assigned-clock-parents = <&sys_clk2_dclk_div>;
		status = "okay";
		gpio-reset = <&gpio5 14 GPIO_ACTIVE_HIGH>;

		AVDD-supply = <&vsys_3v3>;
		IOVDD-supply = <&vsys_3v3>;
		DRVDD-supply = <&vsys_3v3>;
		DVDD-supply = <&vsys_1v8>;
	};
	tlv320aic3106: tlv320aic3106@18 {
		#sound-dai-cells = <0>;
		compatible = "ti,tlv320aic3106";
		reg = <0x18>;
		adc-settle-ms = <40>;
		ai3x-micbias-vg = <1>;		
		assigned-clocks = <&clkoutmux2_clk_mux>;
		assigned-clock-parents = <&sys_clk2_dclk_div>;
		status = "okay";

		AVDD-supply = <&vsys_3v3>;
		IOVDD-supply = <&vsys_3v3>;
		DRVDD-supply = <&vsys_3v3>;
		DVDD-supply = <&vsys_1v8>;
	};
	gpio_csi2_adap: tca6416@20 {
		status = "okay";
		compatible = "ti,tca6416";
		reg = <0x20>;
		gpio-controller;
		#gpio-cells = <2>;
	};

	ov490@36 {
		compatible = "ovti,ov490";
		reg = <0x36>;

		mux-gpios = <&gpio_csi2_adap 0	GPIO_ACTIVE_LOW>,
			    <&gpio_csi2_adap 1	GPIO_ACTIVE_HIGH>,
			    <&gpio_csi2_adap 3	GPIO_ACTIVE_HIGH>,
			    <&gpio_csi2_adap 4	GPIO_ACTIVE_LOW>;
		port {
			csi2_cam0: endpoint@0 {
				clock-lanes = <0>;
				data-lanes = <1 2>;
				remote-endpoint = <&csi2_phy0>;
			};
		};
	};
*/

	tmp112: tmp112@48 {
		compatible = "ti,tmp102";
		reg = <0x48>;
	};
};

&mcspi1 {
	pinctrl-names = "default";
	pinctrl-0 = <&mcspi1_pins_default>;
	status = "okay";
	ti,pindir-d0-out-d1-in;
	ti,spi-num-cs = <1>;

/*
	spidev1: spi@0 {
		compatible = "rohm,dh2228fv";
		reg = <0>;
		spi-max-frequency = <500000>;
	};
*/
	 hi3599@0 {
		 compatible = "hi,hi3599";
		 reg = <0>;
		 interrupt-parent = <&gpio7>;
		 interrupts = <11 0>;
		 irq-gpio = <&gpio7 11 0>;
		 spi-max-frequency = <5000000>;
	 };
};

&mcspi2 {
	pinctrl-names = "default";
	pinctrl-0 = <&mcspi2_pins_default>;
	status = "okay";
	ti,pindir-d0-out-d1-in;
	ti,spi-num-cs = <1>;

/*
	spidev2: spi@0 {
		compatible = "rohm,dh2228fv";
		reg = <0>;
		spi-max-frequency = <500000>;
	};
*/
	 hi8429@0 {
		 compatible = "hi,hi8429";
		 reg = <0>;
		 interrupt-parent = <&gpio5>;
		 interrupts = <6 0>;
		 irq-gpio = <&gpio5 6 0>;
		 rst-gpio = <&gpio5 7 0>;
		 sel0-gpio = <&gpio5 9 0>;
		 sel1-gpio = <&gpio5 8 0>;
		 spi-max-frequency = <5000000>;
	 };
};

&uart1 {
    compatible = "ti,omap2-uart";
	pinctrl-names = "default";
    status = "disabled";
	pinctrl-0 = <&uart1_pins_default>;

    /* GPIO7 pin 25 for data direction */
    //rts-gpio = <&gpio7 25 GPIO_ACTIVE_HIGH>;
    //rs485-rts-active-high;
    //rs485-rts-delay = <1 1>;      /* in milliseconds */
    //linux,rs485-enabled-at-boot-time;
};

&uart6 {
     pinctrl-names = "default";
     status = "disabled";
};
&uart10 {
	pinctrl-names = "default";
	pinctrl-0 = <&uart10_pins_default>;

	status = "disabled";
};



&mcspi3 {
	status = "disabled";
};

&atl {
	assigned-clocks = <&abe_dpll_sys_clk_mux>,
			  <&atl_gfclk_mux>,
			  <&dpll_abe_ck>,
			  <&dpll_abe_m2x2_ck>,
			  <&atl_clkin2_ck>;
	assigned-clock-parents = <&sys_clkin2>, <&dpll_abe_m2_ck>;
	//assigned-clock-rates = <0>, <0>, <180633600>, <361267200>, <5644800>;
	assigned-clock-rates = <0>, <0>, <180633600>, <361267200>, <11289600>;

	status = "okay";

	atl2 {
		bws = <DRA7_ATL_WS_MCASP2_FSX>;
		aws = <DRA7_ATL_WS_MCASP3_FSX>;
	};
};

&mcasp4 {
	#sound-dai-cells = <0>;

	assigned-clocks = <&mcasp4_ahclkx_mux>;
	assigned-clock-parents = <&atl_clkin2_ck>;

	pinctrl-names = "default", "sleep";
	pinctrl-0 = <&mcasp4_pins_default>;
	pinctrl-1 = <&mcasp4_pins_sleep>;
	status = "disabled";

	op-mode = <0>;	/* MCASP_IIS_MODE */
	tdm-slots = <2>;
	/* 4 serializers */
	serial-dir = <	/* 0: INACTIVE, 1: TX, 2: RX */
		1 0 0 0
	>;
	tx-num-evt = <32>;
	rx-num-evt = <32>;
};

&mcasp2 {
	status = "disabled";
	#sound-dai-cells = <0>;

	assigned-clocks = <&mcasp2_ahclkx_mux>;
	assigned-clock-parents = <&sys_clkin2>;

	pinctrl-names = "default";
	pinctrl-0 = <&mcasp2_pins_default>;
	

	op-mode = <0>;	/* MCASP_IIS_MODE */
	tdm-slots = <2>;
	/* 4 serializers */
	serial-dir = <	/* 0: INACTIVE, 1: TX, 2: RX */
		1 2 0 0
		/*1 2 1 2*/
		/*0 0 1 2*/
	>;
	tx-num-evt = <32>;
	rx-num-evt = <32>;
};

&mcasp5 {
	status = "disable";
	#sound-dai-cells = <0>;
	pinctrl-names = "default", "sleep";
	pinctrl-0 = <&mcasp5_pins_default>;
	pinctrl-1 = <&mcasp5_pins_sleep>;

	op-mode = <0>;	/* MCASP_IIS_MODE */
	tdm-slots = <2>;
	/* 4 serializers */
	serial-dir = <	/* 0: INACTIVE, 1: TX, 2: RX */
		1 2 0 0
	>;
	tx-num-evt = <32>;
	rx-num-evt = <32>;
};

&mcasp6 {
	status = "disable";
	#sound-dai-cells = <0>;

	assigned-clocks = <&mcasp6_ahclkx_mux>;
	assigned-clock-parents = <&atl_clkin2_ck>;

	pinctrl-names = "default", "sleep";
	pinctrl-0 = <&mcasp6_pins_default>;
	pinctrl-1 = <&mcasp6_pins_sleep>;

	op-mode = <0>;	/* MCASP_IIS_MODE */
	tdm-slots = <2>;
	/* 4 serializers */
	serial-dir = <	/* 0: INACTIVE, 1: TX, 2: RX */
		1 2 0 0
	>;
	tx-num-evt = <32>;
	rx-num-evt = <32>;
};

&dra7_pmx_core {
	pinctrl-names = "default";
	pinctrl-0 = <&board_pins>;

	board_pins: pinmux_board_pins {
		pinctrl-single,pins = <

			DRA7XX_CORE_IOPAD(0x3724, 0x200e) /*gpio5_13 */
			DRA7XX_CORE_IOPAD(0x34c8, 0x6000e) /*gpio2_24 usb1 id*/  
			DRA7XX_CORE_IOPAD(0x34cc, 0x6000e) /*gpio2_25 usb2 id*/ 
			DRA7XX_CORE_IOPAD(0x3680, 0x90000)/* usb drv */
			DRA7XX_CORE_IOPAD(0x3680, 0xa000e)/* usb drv */
			DRA7XX_CORE_IOPAD(0x371c, 0x4000e) /*gpio2_29 hp det*/

			DRA7XX_CORE_IOPAD(0x37bc, 0x2000e)	/* gpio7_13 wifi wl-reg-on */ 
			DRA7XX_CORE_IOPAD(0x3728, 0x8000e) /* gpio5_14 spk sdn*/
			DRA7XX_CORE_IOPAD(0x3778, 0x20000) /* gpio6_11 camera pwdn*/

			DRA7XX_CORE_IOPAD(0x3774, 0x20000)/* gpio6_10 wdt_enable */
			DRA7XX_CORE_IOPAD(0x3778, 0x20000)/* gpio6_11 wdt_feed */
			DRA7XX_CORE_IOPAD(0x3714, 0x6000e)/* gpio1_4 power_down */
			DRA7XX_CORE_IOPAD(0x36c0, 0x6000e)/* gpio5_5 power_fault */
			DRA7XX_CORE_IOPAD(0x3720, 0x2000e)/* gpio1_5 pwr_4g */
			DRA7XX_CORE_IOPAD(0x3684, 0x8000e)/* gpio6_13 pwr_wifi pull_down*/
			DRA7XX_CORE_IOPAD(0x3580, 0x0000e)/* gpio4_7 wl_en */
			DRA7XX_CORE_IOPAD(0x3584, 0x0000e)/* gpio4_8 h4 */
			DRA7XX_CORE_IOPAD(0x3588, 0x0000e)/* gpio4_9 h4 */
			DRA7XX_CORE_IOPAD(0x3590, 0x0000e)/* gpio4_11 h4 */
			DRA7XX_CORE_IOPAD(0x3594, 0x0000e)/* gpio4_12 h4 */
			DRA7XX_CORE_IOPAD(0x36bc, 0x0000e)/* gpio5_4 h5 */
			DRA7XX_CORE_IOPAD(0x3718, 0x0000e)/* gpio6_7 h5 */
			DRA7XX_CORE_IOPAD(0x3688, 0x00000)/* gpio6_14 h5 */
			DRA7XX_CORE_IOPAD(0x368c, 0x00000)/* gpio6_15 h5 */
			DRA7XX_CORE_IOPAD(0x3470, 0x0000e)/* gpio2_2 h6 */
			DRA7XX_CORE_IOPAD(0x3558, 0x0000e)/* gpio3_29 h6 */
			DRA7XX_CORE_IOPAD(0x37e4, 0x0000e)/* gpio7_23 h6 */
			DRA7XX_CORE_IOPAD(0x36a4, 0x0000e)/* gpio7_31 h6 */
			DRA7XX_CORE_IOPAD(0x3560, 0x2000e)/* gpio3_31 sim_switch*/
			DRA7XX_CORE_IOPAD(0x3564, 0x0000e)/* gpio4_0 pwr_on_off*/
			DRA7XX_CORE_IOPAD(0x3568, 0x1000e)/* gpio4_1 rf_switch*/
			DRA7XX_CORE_IOPAD(0x356c, 0x1000e)/* gpio4_2 4g reset*/
			DRA7XX_CORE_IOPAD(0x3570, 0x6000e)/* gpio4_3 key s3*/
			DRA7XX_CORE_IOPAD(0x3574, 0x6000e)/* gpio4_4 key s2*/
			DRA7XX_CORE_IOPAD(0x37d0, 0x8000e)/* ext emmc enable dcan1_tx.gpio1_14 */
			DRA7XX_CORE_IOPAD(0x3578, 0x0000e)/* gpio4_5 ext emmc pwr pull down*/
			DRA7XX_CORE_IOPAD(0x3818, 0x6000e)/* gpio1_0 rtc int */
			DRA7XX_CORE_IOPAD(0x37d4, 0xe000e)/* gpio1_15 ext emmc key */
			DRA7XX_CORE_IOPAD(0x36c4, 0x5000e)/* gpio5_6 hi8429 int */
			DRA7XX_CORE_IOPAD(0x36c8, 0x1000e)/* gpio5_7 hi8429 rstn */
			DRA7XX_CORE_IOPAD(0x36cc, 0x1000e)/* gpio5_8 hi8429 sel0 */
			DRA7XX_CORE_IOPAD(0x36d0, 0x1000e)/* gpio5_9 hi8429 sel1 */
			DRA7XX_CORE_IOPAD(0x3644, 0x6000e) /*wl int gpio5_17*/
			DRA7XX_CORE_IOPAD(0x371c, 0xa000e) /* gpio2_29 a0 pin*/
			DRA7XX_CORE_IOPAD(0x3690, 0x10000) /* gpio6_16 */
			DRA7XX_CORE_IOPAD(0x369c, 0x1000e) /* gpio6_19 */
		>;
	};

	mmc1_pins_default: mmc1_pins_default {
		pinctrl-single,pins = <
			DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
			DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
			DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
			DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
			DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */
			DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */
			DRA7XX_CORE_IOPAD(0x376c, 0xd000e) /* mmc1_sdcd.gpio6_27 */
			DRA7XX_CORE_IOPAD(0x3770, 0xd000e) /* mmc1_sdwp.gpio6_28 */
		>;
	};

	mmc1_pins_hs: mmc1_pins_hs {
		pinctrl-single,pins = <
			DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
			DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
			DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
			DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
			DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */
			DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */
			DRA7XX_CORE_IOPAD(0x376c, 0xd000e) /* mmc1_sdcd.gpio6_27 */
			DRA7XX_CORE_IOPAD(0x3770, 0xd000e) /* mmc1_sdwp.gpio6_28 */
		>;
	};

	mmc2_pins_default: mmc2_pins_default {
		pinctrl-single,pins = <
			DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */
			DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
			DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
			DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
			DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
			DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
			DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
			DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
			DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
			DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
		>;
	};

	mmc2_pins_hs: mmc2_pins_hs {
		pinctrl-single,pins = <
			DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */
			DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
			DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
			DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
			DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
			DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
			DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
			DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
			DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
			DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
		>;
	};

	mmc2_pins_ddr_1_8v: mmc2_pins_ddr_1_8v {
		pinctrl-single,pins = <
			DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a23.mmc2_clk */
			DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
			DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
			DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
			DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
			DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
			DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
			DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
			DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
			DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
		>;
	};

	mmc3_pins_ds: pinmux_mmc3_pins_ds {
		pinctrl-single,pins = <
			DRA7XX_CORE_IOPAD(0x377c, PIN_INPUT_PULLUP | MUX_MODE0) 	/* mmc3_clk.mmc3_clk */
			DRA7XX_CORE_IOPAD(0x3780, PIN_INPUT_PULLUP | MUX_MODE0) 	/* mmc3_cmd.mmc3_cmd */
			DRA7XX_CORE_IOPAD(0x3784, PIN_INPUT_PULLUP | MUX_MODE0) 	/* mmc3_dat0.mmc3_dat0 */
			DRA7XX_CORE_IOPAD(0x3788, PIN_INPUT_PULLUP | MUX_MODE0) 	/* mmc3_dat1.mmc3_dat1 */
			DRA7XX_CORE_IOPAD(0x378c, PIN_INPUT_PULLUP | MUX_MODE0) 	/* mmc3_dat2.mmc3_dat2 */
			DRA7XX_CORE_IOPAD(0x3790, PIN_INPUT_PULLUP | MUX_MODE0) 	/* mmc3_dat3.mmc3_dat3 */
			DRA7XX_CORE_IOPAD(0x3794, PIN_INPUT_PULLUP | MUX_MODE0) 	/* mmc3_dat4.mmc3_dat4 */
			DRA7XX_CORE_IOPAD(0x3798, PIN_INPUT_PULLUP | MUX_MODE0) 	/* mmc3_dat5.mmc3_dat5 */
			DRA7XX_CORE_IOPAD(0x379c, PIN_INPUT_PULLUP | MUX_MODE0) 	/* mmc3_dat6.mmc3_dat6 */
			DRA7XX_CORE_IOPAD(0x37a0, PIN_INPUT_PULLUP | MUX_MODE0) 	/* mmc3_dat7.mmc3_dat7 */
		>;
	};

	mmc3_pins_sdr12: pinmux_mmc3_pins_sdr12 {
		pinctrl-single,pins = <
			DRA7XX_CORE_IOPAD(0x377c, PIN_INPUT_PULLUP | MUX_MODE0) 	/* mmc3_clk.mmc3_clk */
			DRA7XX_CORE_IOPAD(0x3780, PIN_INPUT_PULLUP | MUX_MODE0) 	/* mmc3_cmd.mmc3_cmd */
			DRA7XX_CORE_IOPAD(0x3784, PIN_INPUT_PULLUP | MUX_MODE0) 	/* mmc3_dat0.mmc3_dat0 */
			DRA7XX_CORE_IOPAD(0x3788, PIN_INPUT_PULLUP | MUX_MODE0) 	/* mmc3_dat1.mmc3_dat1 */
			DRA7XX_CORE_IOPAD(0x378c, PIN_INPUT_PULLUP | MUX_MODE0) 	/* mmc3_dat2.mmc3_dat2 */
			DRA7XX_CORE_IOPAD(0x3790, PIN_INPUT_PULLUP | MUX_MODE0) 	/* mmc3_dat3.mmc3_dat3 */
		>;
	};

	mmc3_pins_hs: pinmux_mmc3_pins_hs {
		pinctrl-single,pins = <
			DRA7XX_CORE_IOPAD(0x377c, PIN_INPUT_PULLUP | MUX_MODE0) 	/* mmc3_clk.mmc3_clk */
			DRA7XX_CORE_IOPAD(0x3780, PIN_INPUT_PULLUP | MUX_MODE0) 	/* mmc3_cmd.mmc3_cmd */
			DRA7XX_CORE_IOPAD(0x3784, PIN_INPUT_PULLUP | MUX_MODE0) 	/* mmc3_dat0.mmc3_dat0 */
			DRA7XX_CORE_IOPAD(0x3788, PIN_INPUT_PULLUP | MUX_MODE0) 	/* mmc3_dat1.mmc3_dat1 */
			DRA7XX_CORE_IOPAD(0x378c, PIN_INPUT_PULLUP | MUX_MODE0) 	/* mmc3_dat2.mmc3_dat2 */
			DRA7XX_CORE_IOPAD(0x3790, PIN_INPUT_PULLUP | MUX_MODE0) 	/* mmc3_dat3.mmc3_dat3 */
		>;
	};

	mmc3_pins_sdr25: pinmux_mmc3_pins_sdr25 {
		pinctrl-single,pins = <
			DRA7XX_CORE_IOPAD(0x377c, PIN_INPUT_PULLUP | MUX_MODE0) 	/* mmc3_clk.mmc3_clk */
			DRA7XX_CORE_IOPAD(0x3780, PIN_INPUT_PULLUP | MUX_MODE0) 	/* mmc3_cmd.mmc3_cmd */
			DRA7XX_CORE_IOPAD(0x3784, PIN_INPUT_PULLUP | MUX_MODE0) 	/* mmc3_dat0.mmc3_dat0 */
			DRA7XX_CORE_IOPAD(0x3788, PIN_INPUT_PULLUP | MUX_MODE0) 	/* mmc3_dat1.mmc3_dat1 */
			DRA7XX_CORE_IOPAD(0x378c, PIN_INPUT_PULLUP | MUX_MODE0) 	/* mmc3_dat2.mmc3_dat2 */
			DRA7XX_CORE_IOPAD(0x3790, PIN_INPUT_PULLUP | MUX_MODE0) 	/* mmc3_dat3.mmc3_dat3 */
		>;
	};

	mmc3_pins_sdr50: pinmux_mmc3_pins_sdr50 {
		pinctrl-single,pins = <
			DRA7XX_CORE_IOPAD(0x377c, PIN_INPUT_PULLUP | 1<<8 | MUX_MODE0) 	/* mmc3_clk.mmc3_clk */
			DRA7XX_CORE_IOPAD(0x3780, PIN_INPUT_PULLUP | 1<<8 | MUX_MODE0) 	/* mmc3_cmd.mmc3_cmd */
			DRA7XX_CORE_IOPAD(0x3784, PIN_INPUT_PULLUP | 1<<8 | MUX_MODE0) 	/* mmc3_dat0.mmc3_dat0 */
			DRA7XX_CORE_IOPAD(0x3788, PIN_INPUT_PULLUP | 1<<8 | MUX_MODE0) 	/* mmc3_dat1.mmc3_dat1 */
			DRA7XX_CORE_IOPAD(0x378c, PIN_INPUT_PULLUP | 1<<8 | MUX_MODE0) 	/* mmc3_dat2.mmc3_dat2 */
			DRA7XX_CORE_IOPAD(0x3790, PIN_INPUT_PULLUP | 1<<8 | MUX_MODE0) 	/* mmc3_dat3.mmc3_dat3 */
		>;
	};

	vout3_ds: pinmux_vout3_ds {
		pinctrl-single,pins = <
			DRA7XX_CORE_IOPAD(0x3464, 0x90003)
			DRA7XX_CORE_IOPAD(0x3460, 0x90003)
			DRA7XX_CORE_IOPAD(0x34bc, 0x90003)
			DRA7XX_CORE_IOPAD(0x3468, 0x90003)
			DRA7XX_CORE_IOPAD(0x3400, 0x90003) /*d0*/
			DRA7XX_CORE_IOPAD(0x3404, 0x90003) /*d1*/
			DRA7XX_CORE_IOPAD(0x3408, 0x90003)
			DRA7XX_CORE_IOPAD(0x340c, 0x90003)
			DRA7XX_CORE_IOPAD(0x3410, 0x90003)
			DRA7XX_CORE_IOPAD(0x3414, 0x90003)
			DRA7XX_CORE_IOPAD(0x3418, 0x90003)
			DRA7XX_CORE_IOPAD(0x341c, 0x90003)
			DRA7XX_CORE_IOPAD(0x3420, 0x90003)
			DRA7XX_CORE_IOPAD(0x3424, 0x90003)
			DRA7XX_CORE_IOPAD(0x3428, 0x90003)
			DRA7XX_CORE_IOPAD(0x342c, 0x90003)
			DRA7XX_CORE_IOPAD(0x3430, 0x90003)
			DRA7XX_CORE_IOPAD(0x3434, 0x90003)
			DRA7XX_CORE_IOPAD(0x3438, 0x90003)
			DRA7XX_CORE_IOPAD(0x343c, 0x90003)
			DRA7XX_CORE_IOPAD(0x3440, 0x90003)
			DRA7XX_CORE_IOPAD(0x3444, 0x90003)
			DRA7XX_CORE_IOPAD(0x3448, 0x90003)
			DRA7XX_CORE_IOPAD(0x344c, 0x90003)
			DRA7XX_CORE_IOPAD(0x3450, 0x90003)
			DRA7XX_CORE_IOPAD(0x3454, 0x90003)
			DRA7XX_CORE_IOPAD(0x3458, 0x90003)
			DRA7XX_CORE_IOPAD(0x345c, 0x90003) /*d23*/


			DRA7XX_CORE_IOPAD(0x346c, 0x2000e)/* lcd pwr gpio2_1 */
		>;
	};
	vout2_ds: pinmux_vout2_ds {
		pinctrl-single,pins = <
			DRA7XX_CORE_IOPAD(0x3564, 0x90104)
			DRA7XX_CORE_IOPAD(0x3560, 0x90104)
			DRA7XX_CORE_IOPAD(0x355c, 0x90104)
			DRA7XX_CORE_IOPAD(0x3558, 0x90104)
			/*DRA7XX_CORE_IOPAD(0x3558, 0x2000e) de*/
			DRA7XX_CORE_IOPAD(0x35c4, 0x90104) /*d0*/
			DRA7XX_CORE_IOPAD(0x35c0, 0x90104) /*d1*/
			DRA7XX_CORE_IOPAD(0x35bc, 0x90104)
			DRA7XX_CORE_IOPAD(0x35b8, 0x90104)
			DRA7XX_CORE_IOPAD(0x35b4, 0x90104)
			DRA7XX_CORE_IOPAD(0x35b0, 0x90104)
			DRA7XX_CORE_IOPAD(0x35ac, 0x90104)
			DRA7XX_CORE_IOPAD(0x35a8, 0x90104)
			DRA7XX_CORE_IOPAD(0x35a4, 0x90104)
			DRA7XX_CORE_IOPAD(0x35a0, 0x90104)
			DRA7XX_CORE_IOPAD(0x359c, 0x90104)
			DRA7XX_CORE_IOPAD(0x3598, 0x90104)
			DRA7XX_CORE_IOPAD(0x3594, 0x90104)
			DRA7XX_CORE_IOPAD(0x3590, 0x90104)
			DRA7XX_CORE_IOPAD(0x358c, 0x90104)
			DRA7XX_CORE_IOPAD(0x3588, 0x90104)
			DRA7XX_CORE_IOPAD(0x3584, 0x90104)
			DRA7XX_CORE_IOPAD(0x3580, 0x90104)
			DRA7XX_CORE_IOPAD(0x357c, 0x90104)
			DRA7XX_CORE_IOPAD(0x3578, 0x90104)
			DRA7XX_CORE_IOPAD(0x3574, 0x90104)
			DRA7XX_CORE_IOPAD(0x3570, 0x90104)
			DRA7XX_CORE_IOPAD(0x356c, 0x90104)
			DRA7XX_CORE_IOPAD(0x3568, 0x90104) /*d23*/

		>;
	};


	i2c3_pins_default: i2c3_pins_default {
		pinctrl-single,pins = <
			DRA7XX_CORE_IOPAD(0x34c0, 0x50008)
			DRA7XX_CORE_IOPAD(0x34c4, 0x50008)
		>;
	};

	i2c4_pins_default: i2c4_pins_default {
		pinctrl-single,pins = <
			DRA7XX_CORE_IOPAD(0x36b0, 0x5000a)
			DRA7XX_CORE_IOPAD(0x36ac, 0x5000a)
			DRA7XX_CORE_IOPAD(0x34d4, 0x6000E)/*tp int gpio2_27*/
		>;
	};

	tp_pin: pinmux_tp_pin {
		pinctrl-single,pins = <
			DRA7XX_CORE_IOPAD(0x34d4, 0x6000E)/*tp int gpio2_27*/
		>;
	};

	mcasp2_pins_default: mcasp2_pins_default {
		pinctrl-single,pins = <
			DRA7XX_CORE_IOPAD(0x3698, 0x50003)
			DRA7XX_CORE_IOPAD(0x36f4, 0x50000)
			DRA7XX_CORE_IOPAD(0x36f8, 0xd0000)
			DRA7XX_CORE_IOPAD(0x3704, 0x50000)
			DRA7XX_CORE_IOPAD(0x3708, 0x50000)
			DRA7XX_CORE_IOPAD(0x370c, 0xd0000)
			DRA7XX_CORE_IOPAD(0x3710, 0xd0000)
			DRA7XX_CORE_IOPAD(0x3694, 0x00009)/* ahclk_clkout2 */
		>;
	};

	mcasp3_pins_default: mcasp3_pins_default {
		pinctrl-single,pins = <
			DRA7XX_CORE_IOPAD(0x3728, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp3_fsx.mcasp3_fsx */
			DRA7XX_CORE_IOPAD(0x372c, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mcasp3_axr0.mcasp3_axr0 */
			DRA7XX_CORE_IOPAD(0x3730, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp3_axr1.mcasp3_axr1 */
		>;
	};

	mcasp3_pins_sleep: mcasp3_pins_sleep {
		pinctrl-single,pins = <
			DRA7XX_CORE_IOPAD(0x3728, PIN_INPUT | MUX_MODE15)
			DRA7XX_CORE_IOPAD(0x372c, PIN_INPUT | MUX_MODE15)
			DRA7XX_CORE_IOPAD(0x3730, PIN_INPUT | MUX_MODE15)
		>;
	};
	mcasp4_pins_default: mcasp4_pins_default {
		pinctrl-single,pins = <
			DRA7XX_CORE_IOPAD(0x3734, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp3_aclkx.mcasp3_aclkx */
			DRA7XX_CORE_IOPAD(0x3738, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp3_fsx.mcasp3_fsx */
			DRA7XX_CORE_IOPAD(0x373c, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mcasp3_axr0.mcasp3_axr0 */
			DRA7XX_CORE_IOPAD(0x3740, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp3_axr1.mcasp3_axr1 */
			DRA7XX_CORE_IOPAD(0x36a0, PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* xref_clk2.mcasp3_ahclkx */
		>;
	};

	mcasp4_pins_sleep: mcasp4_pins_sleep {
		pinctrl-single,pins = <
			DRA7XX_CORE_IOPAD(0x3734, PIN_INPUT | MUX_MODE15)
			DRA7XX_CORE_IOPAD(0x3738, PIN_INPUT | MUX_MODE15)
			DRA7XX_CORE_IOPAD(0x373c, PIN_INPUT | MUX_MODE15)
			DRA7XX_CORE_IOPAD(0x3740, PIN_INPUT | MUX_MODE15)
		>;
	};

	mcasp5_pins_default: mcasp5_pins_default {
		pinctrl-single,pins = <
			DRA7XX_CORE_IOPAD(0x3744, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp5_aclkx.mcasp5_aclkx*/
			DRA7XX_CORE_IOPAD(0x3748, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp5_fsx.mcasp5_fsx*/
			DRA7XX_CORE_IOPAD(0x374c, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mcasp5_axr0.mcasp5_axr0*/
			DRA7XX_CORE_IOPAD(0x3750, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp5_axr1.mcasp5_axr1*/
			DRA7XX_CORE_IOPAD(0x3694, PIN_OUTPUT_PULLDOWN | MUX_MODE4) /* xref_clk0.mcasp5_ahclkx*/
		>;
	};

	mcasp5_pins_sleep: mcasp5_pins_sleep {
		pinctrl-single,pins = <
			DRA7XX_CORE_IOPAD(0x3744, PIN_INPUT | MUX_MODE15)
			DRA7XX_CORE_IOPAD(0x3748, PIN_INPUT | MUX_MODE15)
			DRA7XX_CORE_IOPAD(0x374c, PIN_INPUT | MUX_MODE15)
			DRA7XX_CORE_IOPAD(0x3750, PIN_INPUT | MUX_MODE15)
			DRA7XX_CORE_IOPAD(0x3694, PIN_INPUT | MUX_MODE15)
		>;
	};

	mcasp6_pins_default: mcasp6_pins_default {
		pinctrl-single,pins = <
			DRA7XX_CORE_IOPAD(0x36dc, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mcasp1_axr10.mcasp6_aclkx*/
			DRA7XX_CORE_IOPAD(0x36e0, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mcasp1_axr11.mcasp6_fsx*/
			DRA7XX_CORE_IOPAD(0x36d4, PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mcasp1_axr8.mcasp6_axr0*/
			DRA7XX_CORE_IOPAD(0x36d8, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mcasp1_axr9.mcasp6_axr1*/
			DRA7XX_CORE_IOPAD(0x3698, PIN_OUTPUT_PULLDOWN | MUX_MODE4) /* xref_clk1.mcasp6_ahclkx*/
		>;
	};

	mcasp6_pins_sleep: mcasp6_pins_sleep {
		pinctrl-single,pins = <
			DRA7XX_CORE_IOPAD(0x36dc, PIN_INPUT | MUX_MODE15)
			DRA7XX_CORE_IOPAD(0x36e0, PIN_INPUT | MUX_MODE15)
			DRA7XX_CORE_IOPAD(0x36d4, PIN_INPUT | MUX_MODE15)
			DRA7XX_CORE_IOPAD(0x36d8, PIN_INPUT | MUX_MODE15)
			DRA7XX_CORE_IOPAD(0x3698, PIN_INPUT | MUX_MODE15)
		>;
	};

	mcspi1_pins_default: mcspi1_pins_default {
		pinctrl-single,pins = <
			DRA7XX_CORE_IOPAD(0x37a4, 0x50000)
			DRA7XX_CORE_IOPAD(0x37b0, 0x50000)
			DRA7XX_CORE_IOPAD(0x37ac, 0x50000)
			DRA7XX_CORE_IOPAD(0x37a8, 0x50000)
			DRA7XX_CORE_IOPAD(0x37b4, 0x6000e) /*gpio7_11 hi3599 flag*/
		>;
	};

	mcspi2_pins_default: mcspi2_pins_default {
		pinctrl-single,pins = <
			DRA7XX_CORE_IOPAD(0x37c0, 0x50000)
			DRA7XX_CORE_IOPAD(0x37c8, 0x50000)
			DRA7XX_CORE_IOPAD(0x37c4, 0x50000)
			DRA7XX_CORE_IOPAD(0x37cc, 0x50000)
		>;
	};

	uart1_pins_default: uart1_pins_default {
		pinctrl-single,pins = <
			DRA7XX_CORE_IOPAD(0x37e0, 0xd0000)
			/*DRA7XX_CORE_IOPAD(0x37ec, 0x20000)*/
		>;
	};

	uart4_pins_default: uart4_pins_default {
		pinctrl-single,pins = <
			DRA7XX_CORE_IOPAD(0x373c, 0x50004)
			DRA7XX_CORE_IOPAD(0x3740, 0x10004)
		>;
	};

	uart10_pins_default: uart10_pins_default {
		pinctrl-single,pins = <
			DRA7XX_CORE_IOPAD(0x379c, 0x50002) /*uart10 cts*/
			DRA7XX_CORE_IOPAD(0x37a0, 0x10002) /*uart10 rts*/
		>;
	};



	cpsw_pins_default: cpsw_pins_default {
		pinctrl-single,pins = <
			/* Slave at addr 0x0 */
			DRA7XX_CORE_IOPAD(0x3660, 0x50101) /*rgmii0_txd1 rmii0_rxd1*/
			DRA7XX_CORE_IOPAD(0x3664, 0x50101) /*rgmii0_txd0   rmii0_rxd0*/
			DRA7XX_CORE_IOPAD(0x367c, 0x10001) /*rgmii0_rxd0   rmii0_txd0*/
			DRA7XX_CORE_IOPAD(0x3678, 0x10001) /*rgmii0_rxd1   rmii0_txd1*/
			DRA7XX_CORE_IOPAD(0x365c, 0x50101) /*rgmii0_txd2   rmii0_rxer*/
			DRA7XX_CORE_IOPAD(0x3658, 0x50101) /*rgmii0_txd3   rmii0_crs*/
			DRA7XX_CORE_IOPAD(0x3674, 0x10001) /*rgmii0_rxd2   rmii0_txen*/

			/* Slave at addr 0x1 */
		>;
	};

	cpsw_pins_sleep: cpsw_pins_sleep {
		pinctrl-single,pins = <
			/* Slave 1 */
			DRA7XX_CORE_IOPAD(0x3660, PIN_INPUT | MUX_MODE15)
			DRA7XX_CORE_IOPAD(0x3664, PIN_INPUT | MUX_MODE15)
			DRA7XX_CORE_IOPAD(0x367c, PIN_INPUT | MUX_MODE15)
			DRA7XX_CORE_IOPAD(0x3678, PIN_INPUT | MUX_MODE15)
			DRA7XX_CORE_IOPAD(0x365c, PIN_INPUT | MUX_MODE15)
			DRA7XX_CORE_IOPAD(0x3658, PIN_INPUT | MUX_MODE15)
			DRA7XX_CORE_IOPAD(0x3674, PIN_INPUT | MUX_MODE15)

			/* Slave 2 */
		>;
	};

	davinci_mdio_pins_default: davinci_mdio_pins_default {
		pinctrl-single,pins = <
			/* MDIO */
			DRA7XX_CORE_IOPAD(0x363c, PIN_OUTPUT_PULLUP | MUX_MODE0)
			DRA7XX_CORE_IOPAD(0x3640, PIN_INPUT_PULLUP | MUX_MODE0)
		>;
	};

	davinci_mdio_pins_sleep: davinci_mdio_pins_sleep {
		pinctrl-single,pins = <
			DRA7XX_CORE_IOPAD(0x363c, PIN_INPUT | MUX_MODE15)
			DRA7XX_CORE_IOPAD(0x3640, PIN_INPUT | MUX_MODE15)
		>;
	};

	hdmi_pins: pinmux_hdmi_pins {
		pinctrl-single,pins = <
			DRA7XX_CORE_IOPAD(0x3808, PIN_INPUT | MUX_MODE1)	/* i2c2_sda.hdmi1_ddc_scl */
			DRA7XX_CORE_IOPAD(0x380c, PIN_INPUT | MUX_MODE1)	/* i2c2_scl.hdmi1_ddc_sda */
		>;
	};

	mmc4_pins_ds: pinmux_mmc4_pins_ds {
		pinctrl-single,pins = <
			DRA7XX_CORE_IOPAD(0x37e8, PIN_INPUT_PULLUP | MUX_MODE3)
			DRA7XX_CORE_IOPAD(0x37ec, PIN_INPUT_PULLUP | MUX_MODE3)
			DRA7XX_CORE_IOPAD(0x37f0, PIN_INPUT_PULLUP | MUX_MODE3)
			DRA7XX_CORE_IOPAD(0x37f4, PIN_INPUT_PULLUP | MUX_MODE3)
			DRA7XX_CORE_IOPAD(0x37f8, PIN_INPUT_PULLUP | MUX_MODE3)
			DRA7XX_CORE_IOPAD(0x37fc, PIN_INPUT_PULLUP | MUX_MODE3)
		>;
	};

	mmc4_pins_default: mmc4_pins_default {
		pinctrl-single,pins = <
			DRA7XX_CORE_IOPAD(0x37e8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart1_ctsn.mmc4_clk */
			DRA7XX_CORE_IOPAD(0x37ec, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart1_rtsn.mmc4_cmd */
			DRA7XX_CORE_IOPAD(0x37f0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_rxd.mmc4_dat0 */
			DRA7XX_CORE_IOPAD(0x37f4, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_txd.mmc4_dat1 */
			DRA7XX_CORE_IOPAD(0x37f8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_ctsn.mmc4_dat2 */
			DRA7XX_CORE_IOPAD(0x37fc, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_rtsn.mmc4_dat3 */
		>;
	};

	mmc4_pins_hs: mmc4_pins_hs {
		pinctrl-single,pins = <
			DRA7XX_CORE_IOPAD(0x37e8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart1_ctsn.mmc4_clk */
			DRA7XX_CORE_IOPAD(0x37ec, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart1_rtsn.mmc4_cmd */
			DRA7XX_CORE_IOPAD(0x37f0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_rxd.mmc4_dat0 */
			DRA7XX_CORE_IOPAD(0x37f4, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_txd.mmc4_dat1 */
			DRA7XX_CORE_IOPAD(0x37f8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_ctsn.mmc4_dat2 */
			DRA7XX_CORE_IOPAD(0x37fc, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_rtsn.mmc4_dat3 */
		>;
	};

	mmc4_pins_sdr12: mmc4_pins_sdr12 {
		pinctrl-single,pins = <
			DRA7XX_CORE_IOPAD(0x37e8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart1_ctsn.mmc4_clk */
			DRA7XX_CORE_IOPAD(0x37ec, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart1_rtsn.mmc4_cmd */
			DRA7XX_CORE_IOPAD(0x37f0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_rxd.mmc4_dat0 */
			DRA7XX_CORE_IOPAD(0x37f4, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_txd.mmc4_dat1 */
			DRA7XX_CORE_IOPAD(0x37f8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_ctsn.mmc4_dat2 */
			DRA7XX_CORE_IOPAD(0x37fc, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_rtsn.mmc4_dat3 */
		>;
	};

	mmc4_pins_sdr25: mmc4_pins_sdr25 {
		pinctrl-single,pins = <
			DRA7XX_CORE_IOPAD(0x37e8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart1_ctsn.mmc4_clk */
			DRA7XX_CORE_IOPAD(0x37ec, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart1_rtsn.mmc4_cmd */
			DRA7XX_CORE_IOPAD(0x37f0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_rxd.mmc4_dat0 */
			DRA7XX_CORE_IOPAD(0x37f4, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_txd.mmc4_dat1 */
			DRA7XX_CORE_IOPAD(0x37f8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_ctsn.mmc4_dat2 */
			DRA7XX_CORE_IOPAD(0x37fc, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_rtsn.mmc4_dat3 */
		>;
	};
};

&dra7_iodelay_core {
	mmc1_iodelay_ddr50_conf: mmc1_iodelay_ddr50_conf {
		pinctrl-pin-array = <
			0x618 A_DELAY_PS(0) G_DELAY_PS(0)		/* CFG_MMC1_CLK_IN */
			0x624 A_DELAY_PS(0) G_DELAY_PS(0)		/* CFG_MMC1_CMD_IN */
			0x630 A_DELAY_PS(495) G_DELAY_PS(0)	/* CFG_MMC1_DAT0_IN */
			0x63C A_DELAY_PS(116) G_DELAY_PS(0)	/* CFG_MMC1_DAT1_IN */
			0x648 A_DELAY_PS(117) G_DELAY_PS(0)	/* CFG_MMC1_DAT2_IN */
			0x654 A_DELAY_PS(32) G_DELAY_PS(0)	/* CFG_MMC1_DAT3_IN */
			0x620 A_DELAY_PS(1224) G_DELAY_PS(0)	/* CFG_MMC1_CLK_OUT */
			0x62C A_DELAY_PS(0) G_DELAY_PS(0)		/* CFG_MMC1_CMD_OUT */
			0x638 A_DELAY_PS(44) G_DELAY_PS(0)	/* CFG_MMC1_DAT0_OUT */
			0x644 A_DELAY_PS(64) G_DELAY_PS(0)	/* CFG_MMC1_DAT1_OUT */
			0x650 A_DELAY_PS(79) G_DELAY_PS(0)	/* CFG_MMC1_DAT2_OUT */
			0x65C A_DELAY_PS(87) G_DELAY_PS(0)	/* CFG_MMC1_DAT3_OUT */
			0x628 A_DELAY_PS(0) G_DELAY_PS(0)		/* CFG_MMC1_CMD_OEN */
			0x634 A_DELAY_PS(0) G_DELAY_PS(0)		/* CFG_MMC1_DAT0_OEN */
			0x640 A_DELAY_PS(0) G_DELAY_PS(0)		/* CFG_MMC1_DAT1_OEN */
			0x64C A_DELAY_PS(0) G_DELAY_PS(0)		/* CFG_MMC1_DAT2_OEN */
			0x658 A_DELAY_PS(0) G_DELAY_PS(0)		/* CFG_MMC1_DAT3_OEN */
		>;
	};

	mmc1_iodelay_sdr104_conf: mmc1_iodelay_sdr104_conf {
		pinctrl-pin-array = <
			0x620 A_DELAY_PS(520) G_DELAY_PS(320)	/* CFG_MMC1_CLK_OUT */
			0x62c A_DELAY_PS(0) G_DELAY_PS(0)		/* CFG_MMC1_CMD_OUT */
			0x638 A_DELAY_PS(40) G_DELAY_PS(0)	/* CFG_MMC1_DAT0_OUT */
			0x644 A_DELAY_PS(83) G_DELAY_PS(0)	/* CFG_MMC1_DAT1_OUT */
			0x650 A_DELAY_PS(98) G_DELAY_PS(0)	/* CFG_MMC1_DAT2_OUT */
			0x65c A_DELAY_PS(106) G_DELAY_PS(0)	/* CFG_MMC1_DAT3_OUT */
			0x628 A_DELAY_PS(51) G_DELAY_PS(0)	/* CFG_MMC1_CMD_OEN */
			0x634 A_DELAY_PS(0) G_DELAY_PS(0)		/* CFG_MMC1_DAT0_OEN */
			0x640 A_DELAY_PS(363) G_DELAY_PS(0)	/* CFG_MMC1_DAT1_OEN */
			0x64c A_DELAY_PS(199) G_DELAY_PS(0)	/* CFG_MMC1_DAT2_OEN */
			0x658 A_DELAY_PS(273) G_DELAY_PS(0)	/* CFG_MMC1_DAT3_OEN */
		>;
	};

	mmc2_iodelay_ddr_1_8v_conf: mmc2_iodelay_ddr_1_8v_conf {
		pinctrl-pin-array = <
			0x18c A_DELAY_PS(0) G_DELAY_PS(0)		/* CFG_GPMC_A19_IN */
			0x1a4 A_DELAY_PS(121) G_DELAY_PS(0)	/* CFG_GPMC_A20_IN */
			0x1b0 A_DELAY_PS(0) G_DELAY_PS(0)		/* CFG_GPMC_A21_IN */
			0x1bc A_DELAY_PS(20) G_DELAY_PS(0)	/* CFG_GPMC_A22_IN */
			0x1c8 A_DELAY_PS(108) G_DELAY_PS(0)	/* CFG_GPMC_A23_IN */
			0x1d4 A_DELAY_PS(31) G_DELAY_PS(0)	/* CFG_GPMC_A24_IN */
			0x1e0 A_DELAY_PS(0) G_DELAY_PS(0)		/* CFG_GPMC_A25_IN */
			0x1ec A_DELAY_PS(24) G_DELAY_PS(0)	/* CFG_GPMC_A26_IN */
			0x1f8 A_DELAY_PS(0) G_DELAY_PS(0)		/* CFG_GPMC_A27_IN */
			0x360 A_DELAY_PS(0) G_DELAY_PS(0)		/* CFG_GPMC_CS1_IN */
			0x194 A_DELAY_PS(152) G_DELAY_PS(0)	/* CFG_GPMC_A19_OUT */
			0x1ac A_DELAY_PS(206) G_DELAY_PS(0)	/* CFG_GPMC_A20_OUT */
			0x1b8 A_DELAY_PS(78) G_DELAY_PS(0)	/* CFG_GPMC_A21_OUT */
			0x1c4 A_DELAY_PS(2) G_DELAY_PS(0)		/* CFG_GPMC_A22_OUT */
			0x1d0 A_DELAY_PS(266) G_DELAY_PS(0)	/* CFG_GPMC_A23_OUT */
			0x1dc A_DELAY_PS(0) G_DELAY_PS(0)		/* CFG_GPMC_A24_OUT */
			0x1e8 A_DELAY_PS(0) G_DELAY_PS(0)		/* CFG_GPMC_A25_OUT */
			0x1f4 A_DELAY_PS(43) G_DELAY_PS(0)	/* CFG_GPMC_A26_OUT */
			0x200 A_DELAY_PS(0) G_DELAY_PS(0)		/* CFG_GPMC_A27_OUT */
			0x368 A_DELAY_PS(0) G_DELAY_PS(0)		/* CFG_GPMC_CS1_OUT */
			0x190 A_DELAY_PS(0) G_DELAY_PS(0)		/* CFG_GPMC_A19_OEN */
			0x1a8 A_DELAY_PS(0) G_DELAY_PS(0)		/* CFG_GPMC_A20_OEN */
			0x1b4 A_DELAY_PS(0) G_DELAY_PS(0)		/* CFG_GPMC_A21_OEN */
			0x1c0 A_DELAY_PS(0) G_DELAY_PS(0)		/* CFG_GPMC_A22_OEN */
			0x1d8 A_DELAY_PS(0) G_DELAY_PS(0)		/* CFG_GPMC_A24_OEN */
			0x1e4 A_DELAY_PS(0) G_DELAY_PS(0)		/* CFG_GPMC_A25_OEN */
			0x1f0 A_DELAY_PS(0) G_DELAY_PS(0)		/* CFG_GPMC_A26_OEN */
			0x1fc A_DELAY_PS(0) G_DELAY_PS(0)		/* CFG_GPMC_A27_OEN */
			0x364 A_DELAY_PS(0) G_DELAY_PS(0)		/* CFG_GPMC_CS1_OEN */
		>;
	};

	mmc3_iodelay_sdr50_rev20_conf: mmc3_iodelay_sdr50_rev20_conf {
		pinctrl-single,pins = <
			0x678 (A_DELAY_PS(1085) | G_DELAY_PS(21)) 	/* CFG_MMC3_CLK_IN */
			0x680 (A_DELAY_PS(1269) | G_DELAY_PS(0)) 	/* CFG_MMC3_CLK_OUT */
			0x684 (A_DELAY_PS(0) | G_DELAY_PS(0)) 	/* CFG_MMC3_CMD_IN */
			0x688 (A_DELAY_PS(128) | G_DELAY_PS(0)) 	/* CFG_MMC3_CMD_OEN */
			0x68C (A_DELAY_PS(98) | G_DELAY_PS(0)) 	/* CFG_MMC3_CMD_OUT */
			0x690 (A_DELAY_PS(0) | G_DELAY_PS(0)) 	/* CFG_MMC3_DAT0_IN */
			0x694 (A_DELAY_PS(362) | G_DELAY_PS(0)) 	/* CFG_MMC3_DAT0_OEN */
			0x698 (A_DELAY_PS(0) | G_DELAY_PS(0)) 	/* CFG_MMC3_DAT0_OUT */
			0x69C (A_DELAY_PS(7) | G_DELAY_PS(0)) 	/* CFG_MMC3_DAT1_IN */
			0x6A0 (A_DELAY_PS(333) | G_DELAY_PS(0)) 	/* CFG_MMC3_DAT1_OEN */
			0x6A4 (A_DELAY_PS(0) | G_DELAY_PS(0)) 	/* CFG_MMC3_DAT1_OUT */
			0x6A8 (A_DELAY_PS(0) | G_DELAY_PS(0)) 	/* CFG_MMC3_DAT2_IN */
			0x6AC (A_DELAY_PS(402) | G_DELAY_PS(0)) 	/* CFG_MMC3_DAT2_OEN */
			0x6B0 (A_DELAY_PS(0) | G_DELAY_PS(0)) 	/* CFG_MMC3_DAT2_OUT */
			0x6B4 (A_DELAY_PS(203) | G_DELAY_PS(0)) 	/* CFG_MMC3_DAT3_IN */
			0x6B8 (A_DELAY_PS(549) | G_DELAY_PS(0)) 	/* CFG_MMC3_DAT3_OEN */
			0x6BC (A_DELAY_PS(1) | G_DELAY_PS(0)) 	/* CFG_MMC3_DAT3_OUT */
		>;
	};

	mmc4_iodelay_ds_rev11_conf: mmc4_iodelay_ds_rev11_conf {
		pinctrl-pin-array = <
			0x840 A_DELAY_PS(0) G_DELAY_PS(0)		/* CFG_UART1_CTSN_IN */
			0x848 A_DELAY_PS(0) G_DELAY_PS(0)		/* CFG_UART1_CTSN_OUT */
			0x84c A_DELAY_PS(96) G_DELAY_PS(0)	/* CFG_UART1_RTSN_IN */
			0x850 A_DELAY_PS(0) G_DELAY_PS(0)		/* CFG_UART1_RTSN_OEN */
			0x854 A_DELAY_PS(0) G_DELAY_PS(0)		/* CFG_UART1_RTSN_OUT */
			0x870 A_DELAY_PS(582) G_DELAY_PS(0)	/* CFG_UART2_CTSN_IN */
			0x874 A_DELAY_PS(0) G_DELAY_PS(0)		/* CFG_UART2_CTSN_OEN */
			0x878 A_DELAY_PS(0) G_DELAY_PS(0)		/* CFG_UART2_CTSN_OUT */
			0x87c A_DELAY_PS(391) G_DELAY_PS(0)	/* CFG_UART2_RTSN_IN */
			0x880 A_DELAY_PS(0) G_DELAY_PS(0)		/* CFG_UART2_RTSN_OEN */
			0x884 A_DELAY_PS(0) G_DELAY_PS(0)		/* CFG_UART2_RTSN_OUT */
			0x888 A_DELAY_PS(561) G_DELAY_PS(0)	/* CFG_UART2_RXD_IN */
			0x88c A_DELAY_PS(0) G_DELAY_PS(0)		/* CFG_UART2_RXD_OEN */
			0x890 A_DELAY_PS(0) G_DELAY_PS(0)		/* CFG_UART2_RXD_OUT */
			0x894 A_DELAY_PS(588) G_DELAY_PS(0)	/* CFG_UART2_TXD_IN */
			0x898 A_DELAY_PS(0) G_DELAY_PS(0)		/* CFG_UART2_TXD_OEN */
			0x89c A_DELAY_PS(0) G_DELAY_PS(0)		/* CFG_UART2_TXD_OUT */
		>;
	};

	mmc4_iodelay_ds_rev20_conf: mmc4_iodelay_ds_rev20_conf {
		pinctrl-pin-array = <
			0x840 A_DELAY_PS(0) G_DELAY_PS(0)		/* CFG_UART1_CTSN_IN */
			0x848 A_DELAY_PS(0) G_DELAY_PS(0)		/* CFG_UART1_CTSN_OUT */
			0x84c A_DELAY_PS(307) G_DELAY_PS(0)	/* CFG_UART1_RTSN_IN */
			0x850 A_DELAY_PS(0) G_DELAY_PS(0)		/* CFG_UART1_RTSN_OEN */
			0x854 A_DELAY_PS(0) G_DELAY_PS(0)		/* CFG_UART1_RTSN_OUT */
			0x870 A_DELAY_PS(785) G_DELAY_PS(0)	/* CFG_UART2_CTSN_IN */
			0x874 A_DELAY_PS(0) G_DELAY_PS(0)		/* CFG_UART2_CTSN_OEN */
			0x878 A_DELAY_PS(0) G_DELAY_PS(0)		/* CFG_UART2_CTSN_OUT */
			0x87c A_DELAY_PS(613) G_DELAY_PS(0)	/* CFG_UART2_RTSN_IN */
			0x880 A_DELAY_PS(0) G_DELAY_PS(0)		/* CFG_UART2_RTSN_OEN */
			0x884 A_DELAY_PS(0) G_DELAY_PS(0)		/* CFG_UART2_RTSN_OUT */
			0x888 A_DELAY_PS(683) G_DELAY_PS(0)	/* CFG_UART2_RXD_IN */
			0x88c A_DELAY_PS(0) G_DELAY_PS(0)		/* CFG_UART2_RXD_OEN */
			0x890 A_DELAY_PS(0) G_DELAY_PS(0)		/* CFG_UART2_RXD_OUT */
			0x894 A_DELAY_PS(835) G_DELAY_PS(0)	/* CFG_UART2_TXD_IN */
			0x898 A_DELAY_PS(0) G_DELAY_PS(0)		/* CFG_UART2_TXD_OEN */
			0x89c A_DELAY_PS(0) G_DELAY_PS(0)		/* CFG_UART2_TXD_OUT */
		>;
	};

	mmc4_iodelay_sdr12_hs_sdr25_rev11_conf: mmc4_iodelay_sdr12_hs_sdr25_rev11_conf {
		pinctrl-pin-array = <
			0x840 A_DELAY_PS(0) G_DELAY_PS(0)		/* CFG_UART1_CTSN_IN */
			0x848 A_DELAY_PS(2651) G_DELAY_PS(0)	/* CFG_UART1_CTSN_OUT */
			0x84c A_DELAY_PS(1572) G_DELAY_PS(0)	/* CFG_UART1_RTSN_IN */
			0x850 A_DELAY_PS(0) G_DELAY_PS(0)		/* CFG_UART1_RTSN_OEN */
			0x854 A_DELAY_PS(0) G_DELAY_PS(0)		/* CFG_UART1_RTSN_OUT */
			0x870 A_DELAY_PS(1913) G_DELAY_PS(0)	/* CFG_UART2_CTSN_IN */
			0x874 A_DELAY_PS(0) G_DELAY_PS(0)		/* CFG_UART2_CTSN_OEN */
			0x878 A_DELAY_PS(0) G_DELAY_PS(0)		/* CFG_UART2_CTSN_OUT */
			0x87c A_DELAY_PS(1721) G_DELAY_PS(0)	/* CFG_UART2_RTSN_IN */
			0x880 A_DELAY_PS(0) G_DELAY_PS(0)		/* CFG_UART2_RTSN_OEN */
			0x884 A_DELAY_PS(0) G_DELAY_PS(0)		/* CFG_UART2_RTSN_OUT */
			0x888 A_DELAY_PS(1891) G_DELAY_PS(0)	/* CFG_UART2_RXD_IN */
			0x88c A_DELAY_PS(0) G_DELAY_PS(0)		/* CFG_UART2_RXD_OEN */
			0x890 A_DELAY_PS(0) G_DELAY_PS(0)		/* CFG_UART2_RXD_OUT */
			0x894 A_DELAY_PS(1919) G_DELAY_PS(0)	/* CFG_UART2_TXD_IN */
			0x898 A_DELAY_PS(0) G_DELAY_PS(0)		/* CFG_UART2_TXD_OEN */
			0x89c A_DELAY_PS(0) G_DELAY_PS(0)		/* CFG_UART2_TXD_OUT */
		>;
	};

	mmc4_iodelay_sdr12_hs_sdr25_rev20_conf: mmc4_iodelay_sdr12_hs_sdr25_rev20_conf {
		pinctrl-pin-array = <
			0x840 A_DELAY_PS(0) G_DELAY_PS(0)		/* CFG_UART1_CTSN_IN */
			0x848 A_DELAY_PS(1147) G_DELAY_PS(0)	/* CFG_UART1_CTSN_OUT */
			0x84c A_DELAY_PS(1834) G_DELAY_PS(0)	/* CFG_UART1_RTSN_IN */
			0x850 A_DELAY_PS(0) G_DELAY_PS(0)		/* CFG_UART1_RTSN_OEN */
			0x854 A_DELAY_PS(0) G_DELAY_PS(0)		/* CFG_UART1_RTSN_OUT */
			0x870 A_DELAY_PS(2165) G_DELAY_PS(0)	/* CFG_UART2_CTSN_IN */
			0x874 A_DELAY_PS(0) G_DELAY_PS(0)		/* CFG_UART2_CTSN_OEN */
			0x878 A_DELAY_PS(0) G_DELAY_PS(0)		/* CFG_UART2_CTSN_OUT */
			0x87c A_DELAY_PS(1929) G_DELAY_PS(64)	/* CFG_UART2_RTSN_IN */
			0x880 A_DELAY_PS(0) G_DELAY_PS(0)		/* CFG_UART2_RTSN_OEN */
			0x884 A_DELAY_PS(0) G_DELAY_PS(0)		/* CFG_UART2_RTSN_OUT */
			0x888 A_DELAY_PS(1935) G_DELAY_PS(128)	/* CFG_UART2_RXD_IN */
			0x88c A_DELAY_PS(0) G_DELAY_PS(0)		/* CFG_UART2_RXD_OEN */
			0x890 A_DELAY_PS(0) G_DELAY_PS(0)		/* CFG_UART2_RXD_OUT */
			0x894 A_DELAY_PS(2172) G_DELAY_PS(44)	/* CFG_UART2_TXD_IN */
			0x898 A_DELAY_PS(0) G_DELAY_PS(0)		/* CFG_UART2_TXD_OEN */
			0x89c A_DELAY_PS(0) G_DELAY_PS(0)		/* CFG_UART2_TXD_OUT */
		>;
	};
};

&mmc1 {
	pinctrl-names = "default", "hs";
	pinctrl-0 = <&mmc1_pins_default>;
	pinctrl-1 = <&mmc1_pins_hs>;
	/delete-property/ vmmc-supply;
	/delete-property/ vmmc_aux-supply;
	vmmc-supply = <&vsys_3v3>;
	cd-gpios = <&gpio6 27 0>; /* gpio 219 */
	wp-gpios = <&gpio6 28 0>; /* gpio 220 */
};

&mmc2 {
	//pinctrl-names = "default", "hs", "ddr_1_8v";
	pinctrl-names = "default", "hs";
	pinctrl-0 = <&mmc2_pins_default>;
	pinctrl-1 = <&mmc2_pins_hs>;
	//pinctrl-2 = <&mmc2_pins_ddr_1_8v &mmc2_iodelay_ddr_1_8v_conf>;
    /delete-property/ cd-gpios;
    /delete-property/ vmmc-supply;
    /delete-property/ vmmc_aux-supply;
    /delete-property/ mmc-ddr-1_8v;
    /delete-property/ no-1-8-v;
    vmmc-supply = <&vsys_3v3>;
    ti,non-removable;
	bus-width = <8>;
	max-frequency = <96000000>;
};

&mmc3 {
	//pinctrl-names = "default", "hs", "sdr12", "sdr25", "sdr50";
	pinctrl-names = "default", "hs";
	status = "okay";
	pinctrl-0 = <&mmc3_pins_ds>;
	pinctrl-1 = <&mmc3_pins_hs>;
	//pinctrl-2 = <&mmc3_pins_sdr12>;
	//pinctrl-3 = <&mmc3_pins_sdr25>;
	//pinctrl-4 = <&mmc3_pins_sdr50 &mmc3_iodelay_sdr50_rev20_conf>;
	/delete-property/ vmmc-supply;
	/delete-property/ vmmc_aux-supply;
	/delete-property/ mmc-ddr-1_8v;
	/delete-property/ no-1-8-v;
	/delete-property/ sd-uhs-sdr12;
	/delete-property/ sd-uhs-sdr25;
	/delete-property/ sd-uhs-sdr50;
	/delete-property/ ti,non-removable;
	//cd-gpios = <&gpio1 15 1>;
	vmmc-supply = <&emmcex_oe>;
	bus-width = <8>;
	max-frequency = <96000000>;
};

&mmc4 {
	pinctrl-names = "default";
	status = "okay";
	pinctrl-0 = <&mmc4_pins_ds>;
	vmmc-supply = <&vmmcwl_fixed>;
	ti,non-removable;
	ti,needs-special-hs-handling;
	cap-power-off-card;
	keep-power-in-suspend;

	#address-cells = <1>;
	#size-cells = <0>;
	wlcore: wlcore@0 {
		compatible = "ti,wl1807";
		reg = <2>;
		interrupt-parent = <&gpio5>;
		interrupts = <17 IRQ_TYPE_LEVEL_HIGH>;
	};
};

/*&mmc4 {
	status = "okay";
	vmmc-supply = <&vmmcwl_fixed>;
	bus-width = <4>;
	cap-power-off-card;
	keep-power-in-suspend;
	ti,non-removable;
	max-frequency = <400000>;

	pinctrl-names = "default-rev11", "default", "hs-rev11", "hs", "sdr12-rev11", "sdr12", "sdr25-rev11", "sdr25";
	//pinctrl-names = "default";
	pinctrl-0 = <&mmc4_pins_default &mmc4_iodelay_ds_rev11_conf>;
	pinctrl-1 = <&mmc4_pins_default &mmc4_iodelay_ds_rev20_conf>;
	pinctrl-2 = <&mmc4_pins_hs &mmc4_iodelay_sdr12_hs_sdr25_rev11_conf>;
	pinctrl-3 = <&mmc4_pins_hs &mmc4_iodelay_sdr12_hs_sdr25_rev20_conf>;
	pinctrl-4 = <&mmc4_pins_sdr12 &mmc4_iodelay_sdr12_hs_sdr25_rev11_conf>;
	pinctrl-5 = <&mmc4_pins_sdr12 &mmc4_iodelay_sdr12_hs_sdr25_rev20_conf>;
	pinctrl-6 = <&mmc4_pins_sdr25 &mmc4_iodelay_sdr12_hs_sdr25_rev11_conf>;
	pinctrl-7 = <&mmc4_pins_sdr25 &mmc4_iodelay_sdr12_hs_sdr25_rev20_conf>;

	#address-cells = <1>;
	#size-cells = <0>;
	wlcore: wlcore@2 {
		compatible = "ti,wl1807";
		reg = <2>;
		interrupt-parent = <&gpio5>;
		interrupts = <17 IRQ_TYPE_LEVEL_HIGH>;
	};
};*/

&usb2_phy1 {
	phy-supply = <&vsys_3v3>;
};

&usb2_phy2 {
	phy-supply = <&vsys_3v3>;
};

&usb1 {
	//dr_mode = "otg";
	dr_mode = "host";
};

&usb2 {
	dr_mode = "host";
};

&omap_dwc3_1 {
	extcon = <&extcon_usb1>;
};

&omap_dwc3_2 {
	extcon = <&extcon_usb2>;
};

&cpu0 {
	vdd-supply = <&lp8733_buck0_reg>;
};

&ov2659_1 {
	remote-endpoint = <&vin1b>;
};

&vin1b {
	status = "okay";

	endpoint@2 {
		slave-mode;
		remote-endpoint = <&ov2659_1>;
	};
};

&vip1 {
	status = "okay";
};

&mailbox5 {
	status = "okay";
	mbox_ipu1_ipc3x: mbox_ipu1_ipc3x {
		status = "okay";
	};
	mbox_dsp1_ipc3x: mbox_dsp1_ipc3x {
		status = "okay";
	};
};

&mailbox6 {
	status = "okay";
	mbox_ipu2_ipc3x: mbox_ipu2_ipc3x {
		status = "okay";
	};
};

&mmu0_dsp1 {
	status = "okay";
};

&mmu1_dsp1 {
	status = "okay";
};

&mmu_ipu1 {
	status = "okay";
};

&mmu_ipu2 {
	status = "okay";
};

&ipu2 {
	//status = "disable";
	status = "okay";
	memory-region = <&ipu2_cma_pool>;
	mboxes = <&mailbox6 &mbox_ipu2_ipc3x>;
	timers = <&timer3>;
	watchdog-timers = <&timer4>, <&timer9>;
};

&ipu1 {
	status = "okay";
	memory-region = <&ipu1_cma_pool>;
	mboxes = <&mailbox5 &mbox_ipu1_ipc3x>;
	timers = <&timer11>;
	watchdog-timers = <&timer7>, <&timer8>;
};

&dsp1 {
	status = "okay";
	memory-region = <&dsp1_cma_pool>;
	mboxes = <&mailbox5 &mbox_dsp1_ipc3x>;
	timers = <&timer5>;
	watchdog-timers = <&timer10>;
};

&dss {
	pinctrl-names = "default";
	//pinctrl-0 = <&vout2_ds>;
	pinctrl-0 = <&vout3_ds>;
};

&pruss1_mdio {
	reset-gpios = <&gpio5 8 GPIO_ACTIVE_LOW>;
	reset-delay-us = <2>;   /* PHY datasheet states 1uS min */
	pruss1_eth0_phy: ethernet-phy@0 {
		reg = <0>;
		interrupt-parent = <&gpio3>;
		interrupts = <28 IRQ_TYPE_EDGE_FALLING>;
	};

	pruss1_eth1_phy: ethernet-phy@1 {
		reg = <1>;
		interrupt-parent = <&gpio3>;
		interrupts = <29 IRQ_TYPE_EDGE_FALLING>;
	};
};

&pruss2_mdio {
	status = "disabled";
	reset-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
	reset-delay-us = <2>;   /* PHY datasheet states 1uS min */
};

&epwmss1 {
	status = "okay";
};

&ehrpwm1 {
	status = "okay";
};

&dss {
	vdda_video-supply = <&vsys_3v3>;//fixed later pmic
	ports {
        /delete-node/ port@0;
		port@2 {
			reg = <2>;

			dpi_out: endpoint {
				remote-endpoint = <&lcd_in>;
				data-lines = <24>;
			};
		};
    };
};

&hdmi {
	vdda-supply = <&vsys_1v8>;//fixed later pmic
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&hdmi_pins>;

	port {
		hdmi_out: endpoint {
			remote-endpoint = <&hdmi_connector_in>;
		};
	};
};

&hdmi0 {
    status = "disabled";
	pinctrl-names = "default";
	//pinctrl-0 = <&hdmi_conn_pins>;
	//hpd-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;
		port {
			hdmi_connector_in: endpoint {
				remote-endpoint = <&hdmi_out>;
			};
		};
};
&cal {
	status = "okay";
};

/*
&csi2_0 {
	csi2_phy0: endpoint@0 {
		slave-mode;
		remote-endpoint = <&csi2_cam0>;
	};
};
*/

&dcan1 {
	status = "disabled";
};

&dss {
       ti,no-reset-on-init;
       ti,no-idle-on-init;
       ti,no-idle;
       dispc@58001000 {
               ti,no-reset-on-init;
               ti,no-idle-on-init;
               ti,no-idle;
       };
};

&gpio6 {
       ti,no-reset-on-init;
};

    

    


    

    config.bld file
    

    EXT_CODE: {
        name: "EXT_CODE",
        base: 0x95000000,
        len:  0x00100000,
        space: "code",
        access: "RWX"
    },
    EXT_DATA: {
        name: "EXT_DATA",
        base: 0x95100000,
        len:  0x00500000,
        space: "data",
        access: "RW"
    },
    EXT_HEAP: {
        name: "EXT_HEAP",
        base: 0x95600000,
        len:  0x00300000,
        space: "data",
        access: "RW"
    },
    

    



    
    
    
        Fullscreen
        0601.config.bld.txt
        Download
    
    
    
    /*
 * Copyright (c) 2013-2015, Texas Instruments Incorporated
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * *  Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 *
 * *  Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 *
 * *  Neither the name of Texas Instruments Incorporated nor the names of
 *    its contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */

/*
 *  ======== config.bld ========
 *
 */
var Build = xdc.useModule('xdc.bld.BuildEnvironment');

/*  Memory Map for ti.platforms.evmDRA7XX:dsp1 and ti.platforms.evmDRA7XX:dsp2
 *
 *  --- External Memory ---
 *  Virtual     Physical        Size            Comment
 *  ------------------------------------------------------------------------
 *  9500_4000   ????_????    10_0000  (  ~1 MB) EXT_CODE
 *  9510_0000   ????_????    10_0000  (   1 MB) EXT_DATA
 *  9520_0000   ????_????    30_0000  (   3 MB) EXT_HEAP
 *  9F00_0000   9F00_0000     6_0000  ( 384 kB) TRACE_BUF
 *  9F06_0000   9F06_0000     1_0000  (  64 kB) EXC_DATA
 *  9F07_0000   9F07_0000     2_0000  ( 128 kB) PM_DATA (Power mgmt)
 */
var evmDRA7XX_ExtMemMapDsp = {
    EXT_CODE: {
        name: "EXT_CODE",
        base: 0x95000000,
        len:  0x00100000,
        space: "code",
        access: "RWX"
    },
    EXT_DATA: {
        name: "EXT_DATA",
        base: 0x95100000,
        len:  0x00500000,
        space: "data",
        access: "RW"
    },
    EXT_HEAP: {
        name: "EXT_HEAP",
        base: 0x95600000,
        len:  0x00300000,
        space: "data",
        access: "RW"
    },
    TRACE_BUF: {
        name: "TRACE_BUF",
        base: 0x9F000000,
        len:  0x00060000,
        space: "data",
        access: "RW"
    },
    EXC_DATA: {
        name: "EXC_DATA",
        base: 0x9F060000,
        len:  0x00010000,
        space: "data",
        access: "RW"
    },
    PM_DATA: {
        name: "PM_DATA",
        base: 0x9F070000,
        len:  0x00020000,
        space: "data",
        access: "RWX"  /* should this have execute perm? */
    },
};

Build.platformTable["ti.platforms.evmDRA7XX:dsp1"] = {
    externalMemoryMap: [
        [ "EXT_CODE", evmDRA7XX_ExtMemMapDsp.EXT_CODE ],
        [ "EXT_DATA", evmDRA7XX_ExtMemMapDsp.EXT_DATA ],
        [ "EXT_HEAP", evmDRA7XX_ExtMemMapDsp.EXT_HEAP ],
        [ "TRACE_BUF", evmDRA7XX_ExtMemMapDsp.TRACE_BUF ],
        [ "EXC_DATA", evmDRA7XX_ExtMemMapDsp.EXC_DATA ],
        [ "PM_DATA", evmDRA7XX_ExtMemMapDsp.PM_DATA ],
    ],
    codeMemory: "EXT_CODE",
    dataMemory: "EXT_DATA",
    stackMemory: "EXT_DATA",
};
Build.platformTable["ti.platforms.evmDRA7XX:dsp2"] =
	Build.platformTable["ti.platforms.evmDRA7XX:dsp1"];



/*  Memory Map for ti.platforms.evmDRA7XX:ipu2
 *
 *  --- External Memory ---
 *  Virtual     Physical        Size            Comment
 *  ------------------------------------------------------------------------
 *  0000_4000   ????_????    5F_C000  (  ~6 MB) EXT_CODE
 *  8000_0000   ????_????    60_0000  (   6 MB) EXT_DATA
 *  8060_0000   ????_????   960_0000  (  86 MB) EXT_HEAP
 *  9F00_0000   9F00_0000     6_0000  ( 384 kB) TRACE_BUF
 *  9F06_0000   9F06_0000     1_0000  (  64 kB) EXC_DATA
 *  9F07_0000   9F07_0000     2_0000  ( 128 kB) PM_DATA (Power mgmt)
 */
var evmDRA7XX_ExtMemMapIpu2 = {
    EXT_CODE: {
        name: "EXT_CODE",
        base: 0x00004000,
        len:  0x005FC000,
        space: "code",
        access: "RWX"
    },
    EXT_DATA: {
        name: "EXT_DATA",
        base: 0x80000000,
        len:  0x00600000,
        space: "data",
        access: "RW"
    },
    EXT_HEAP: {
        name: "EXT_HEAP",
        base: 0x80600000,
        len:  0x09600000,
        space: "data",
        access: "RW"
    },
    TRACE_BUF: {
        name: "TRACE_BUF",
        base: 0x9F000000,
        len:  0x00060000,
        space: "data",
        access: "RW"
    },
    EXC_DATA: {
        name: "EXC_DATA",
        base: 0x9F060000,
        len:  0x00010000,
        space: "data",
        access: "RW"
    },
    PM_DATA: {
        name: "PM_DATA",
        base: 0x9F070000,
        len:  0x00020000,
        space: "data",
        access: "RWX"  /* should this have execute perm? */
    }
};

Build.platformTable["ti.platforms.evmDRA7XX:ipu2"] = {
    externalMemoryMap: [
        [ "EXT_CODE", evmDRA7XX_ExtMemMapIpu2.EXT_CODE ],
        [ "EXT_DATA", evmDRA7XX_ExtMemMapIpu2.EXT_DATA ],
        [ "EXT_HEAP", evmDRA7XX_ExtMemMapIpu2.EXT_HEAP ],
        [ "TRACE_BUF", evmDRA7XX_ExtMemMapIpu2.TRACE_BUF ],
        [ "EXC_DATA", evmDRA7XX_ExtMemMapIpu2.EXC_DATA ],
        [ "PM_DATA", evmDRA7XX_ExtMemMapIpu2.PM_DATA ]
    ],
    codeMemory: "EXT_CODE",
    dataMemory: "EXT_DATA",
    stackMemory: "EXT_DATA",
};

/*  Memory Map for ti.platforms.evmDRA7XX:ipu1
 *
 *  --- External Memory ---
 *  Virtual     Physical        Size            Comment
 *  ------------------------------------------------------------------------
 *  0000_4000   ????_????     F_C000  (  ~1 MB) EXT_CODE
 *  8000_0000   ????_????    20_0000  (   2 MB) EXT_DATA
 *  8020_0000   ????_????    30_0000  (   3 MB) EXT_HEAP
 *  9F00_0000   9F00_0000     6_0000  ( 384 kB) TRACE_BUF
 *  9F06_0000   9F06_0000     1_0000  (  64 kB) EXC_DATA
 *  9F07_0000   9F07_0000     2_0000  ( 128 kB) PM_DATA (Power mgmt)
 */
var evmDRA7XX_ExtMemMapIpu1 = {
    EXT_CODE: {
        name: "EXT_CODE",
        base: 0x00004000,
        len:  0x000FC000,
        space: "code",
        access: "RWX"
    },
    EXT_DATA: {
        name: "EXT_DATA",
        base: 0x80000000,
        len:  0x00200000,
        space: "data",
        access: "RW"
    },
    EXT_HEAP: {
        name: "EXT_HEAP",
        base: 0x80200000,
        len:  0x00300000,
        space: "data",
        access: "RW"
    },
    TRACE_BUF: {
        name: "TRACE_BUF",
        base: 0x9F000000,
        len:  0x00060000,
        space: "data",
        access: "RW"
    },
    EXC_DATA: {
        name: "EXC_DATA",
        base: 0x9F060000,
        len:  0x00010000,
        space: "data",
        access: "RW"
    },
    PM_DATA: {
        name: "PM_DATA",
        base: 0x9F070000,
        len:  0x00020000,
        space: "data",
        access: "RWX"  /* should this have execute perm? */
    }
};

Build.platformTable["ti.platforms.evmDRA7XX:ipu1"] = {
    externalMemoryMap: [
        [ "EXT_CODE", evmDRA7XX_ExtMemMapIpu1.EXT_CODE ],
        [ "EXT_DATA", evmDRA7XX_ExtMemMapIpu1.EXT_DATA ],
        [ "EXT_HEAP", evmDRA7XX_ExtMemMapIpu1.EXT_HEAP ],
        [ "TRACE_BUF", evmDRA7XX_ExtMemMapIpu1.TRACE_BUF ],
        [ "EXC_DATA", evmDRA7XX_ExtMemMapIpu1.EXC_DATA ],
        [ "PM_DATA", evmDRA7XX_ExtMemMapIpu1.PM_DATA ]
    ],
    codeMemory: "EXT_CODE",
    dataMemory: "EXT_DATA",
    stackMemory: "EXT_DATA",
};

    

    


    

    

    rsc_table_vayu_dsp.c file
    

    #define DSP_MEM_TEXT            0x95000000
/* Co-locate alongside TILER region for easier flushing */
#define DSP_MEM_IOBUFS          0x80000000
#define DSP_MEM_DATA            0x95100000
#define DSP_MEM_HEAP            0x95600000
    

    



    
    
    
        Fullscreen
        rsc_table_vayu_dsp.c .txt
        Download
    
    
    
    /*
 * Copyright (c) 2012-2014, Texas Instruments Incorporated
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * *  Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 *
 * *  Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 *
 * *  Neither the name of Texas Instruments Incorporated nor the names of
 *    its contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */

/*
 *  ======== rsc_table_vayu_dsp.h ========
 *
 *  Define the resource table entries for all DSP cores. This will be
 *  incorporated into corresponding base images, and used by the remoteproc
 *  on the host-side to allocated/reserve resources.
 *
 */

#ifndef _RSC_TABLE_VAYU_DSP_H_
#define _RSC_TABLE_VAYU_DSP_H_

#include "rsc_types.h"

/* DSP Memory Map */
#define L4_DRA7XX_BASE          0x4A000000

#define L4_PERIPHERAL_L4CFG     (L4_DRA7XX_BASE)
#define DSP_PERIPHERAL_L4CFG    0x4A000000

#define L4_PERIPHERAL_L4PER1    0x48000000
#define DSP_PERIPHERAL_L4PER1   0x48000000

#define L4_PERIPHERAL_L4PER2    0x48400000
#define DSP_PERIPHERAL_L4PER2   0x48400000

#define L4_PERIPHERAL_L4PER3    0x48800000
#define DSP_PERIPHERAL_L4PER3   0x48800000

#define L4_PERIPHERAL_L4EMU     0x54000000
#define DSP_PERIPHERAL_L4EMU    0x54000000

#define L3_PERIPHERAL_DMM       0x4E000000
#define DSP_PERIPHERAL_DMM      0x4E000000

#define L3_TILER_MODE_0_1       0x60000000
#define DSP_TILER_MODE_0_1      0x60000000

#define L3_TILER_MODE_2         0x70000000
#define DSP_TILER_MODE_2        0x70000000

#define L3_TILER_MODE_3         0x78000000
#define DSP_TILER_MODE_3        0x78000000

#define DSP_MEM_TEXT            0x95000000
/* Co-locate alongside TILER region for easier flushing */
#define DSP_MEM_IOBUFS          0x80000000
#define DSP_MEM_DATA            0x95100000
#define DSP_MEM_HEAP            0x95600000

#define DSP_MEM_IPC_DATA        0x9F000000
#define DSP_MEM_IPC_VRING       0x99000000
#define DSP_MEM_RPMSG_VRING0    0x99000000
#define DSP_MEM_RPMSG_VRING1    0x99004000
#define DSP_MEM_VRING_BUFS0     0x99040000
#define DSP_MEM_VRING_BUFS1     0x99080000

#define DSP_PERIPHERAL_EDMA     0x43300000
#define L3_PERIPHERAL_EDMA      0x43300000
#define DSP_MCASP1_DATA         0x45800000
#define L3_MCASP1_DATA          0x45800000

#define DSP_MCASP2_DATA         0x45c00000
#define L3_MCASP2_DATA          0x45c00000

#define DSP_DDR_DATA            0x9B000000
#define L3_DDR_DATA             0x9B000000

#define DSP_MEM_IPC_VRING_SIZE  SZ_1M
#define DSP_MEM_IPC_DATA_SIZE   SZ_1M
#define DSP_MEM_TEXT_SIZE       SZ_1M
#define DSP_MEM_DATA_SIZE       (SZ_1M * 5)
#define DSP_MEM_HEAP_SIZE       (SZ_1M * 3)
#define DSP_MEM_IOBUFS_SIZE     (SZ_1M * 90)


/* NOTE: Make sure this matches what is configured in the linux device tree */
#define DSP_CMEM_IOBUFS 0xA0000000
#define PHYS_CMEM_IOBUFS 0xA0000000
#define DSP_CMEM_IOBUFS_SIZE (SZ_1M * 192)
/*
 * Assign fixed RAM addresses to facilitate a fixed MMU table.
 */

//BWC
#define VAYU_DSP_1

/* See CMA BASE addresses in Linux side: arch/arm/mach-omap2/remoteproc.c */
#if defined (VAYU_DSP_1)
#define PHYS_MEM_IPC_VRING      0x99000000
#elif defined (VAYU_DSP_2)
#define PHYS_MEM_IPC_VRING      0x9F000000
#endif

/* Need to be identical to that of IPU */
#define PHYS_MEM_IOBUFS         0xBA300000

/*
 * Sizes of the virtqueues (expressed in number of buffers supported,
 * and must be power of 2)
 */
#define DSP_RPMSG_VQ0_SIZE      256
#define DSP_RPMSG_VQ1_SIZE      256

/* flip up bits whose indices represent features we support */
#define RPMSG_DSP_C0_FEATURES         1

struct my_resource_table {
    struct resource_table base;

    UInt32 offset[21];  /* Should match 'num' in actual definition */

    /* rpmsg vdev entry */
    struct fw_rsc_vdev rpmsg_vdev;
    struct fw_rsc_vdev_vring rpmsg_vring0;
    struct fw_rsc_vdev_vring rpmsg_vring1;

    /* text carveout entry */
    struct fw_rsc_carveout text_cout;

    /* data carveout entry */
    struct fw_rsc_carveout data_cout;

    /* heap carveout entry */
    struct fw_rsc_carveout heap_cout;

    /* ipcdata carveout entry */
    struct fw_rsc_carveout ipcdata_cout;

    /* trace entry */
    struct fw_rsc_trace trace;

    /* devmem entry */
    struct fw_rsc_devmem devmem0;

    /* devmem entry */
    struct fw_rsc_devmem devmem1;

    /* devmem entry */
    struct fw_rsc_devmem devmem2;

    /* devmem entry */
    struct fw_rsc_devmem devmem3;

    /* devmem entry */
    struct fw_rsc_devmem devmem4;

    /* devmem entry */
    struct fw_rsc_devmem devmem5;

    /* devmem entry */
    struct fw_rsc_devmem devmem6;

    /* devmem entry */
    struct fw_rsc_devmem devmem7;

    /* devmem entry */
    struct fw_rsc_devmem devmem8;

    /* devmem entry */
    struct fw_rsc_devmem devmem9;

    /* devmem entry */
    struct fw_rsc_devmem devmem10;
    /* devmem entry */
    struct fw_rsc_devmem devmem11;

    /* devmem entry */
    struct fw_rsc_devmem devmem12;
    /* devmem entry */
        struct fw_rsc_devmem devmem13;
        /* devmem entry */
            struct fw_rsc_devmem devmem14;
};

//BWC added extern declaration
extern char ti_trace_SysMin_Module_State_0_outbuf__A;
#define TRACEBUFADDR (UInt32)&ti_trace_SysMin_Module_State_0_outbuf__A

#pragma DATA_SECTION(ti_ipc_remoteproc_ResourceTable, ".resource_table")
#pragma DATA_ALIGN(ti_ipc_remoteproc_ResourceTable, 4096)

struct my_resource_table ti_ipc_remoteproc_ResourceTable = {
    1,      /* we're the first version that implements this */
    21,     /* number of entries in the table */
    0, 0,   /* reserved, must be zero */
    /* offsets to entries */
    {
        offsetof(struct my_resource_table, rpmsg_vdev),
        offsetof(struct my_resource_table, text_cout),
        offsetof(struct my_resource_table, data_cout),
        offsetof(struct my_resource_table, heap_cout),
        offsetof(struct my_resource_table, ipcdata_cout),
        offsetof(struct my_resource_table, trace),
        offsetof(struct my_resource_table, devmem0),
        offsetof(struct my_resource_table, devmem1),
        offsetof(struct my_resource_table, devmem2),
        offsetof(struct my_resource_table, devmem3),
        offsetof(struct my_resource_table, devmem4),
        offsetof(struct my_resource_table, devmem5),
        offsetof(struct my_resource_table, devmem6),
        offsetof(struct my_resource_table, devmem7),
        offsetof(struct my_resource_table, devmem8),
        offsetof(struct my_resource_table, devmem9),
        offsetof(struct my_resource_table, devmem10),
        offsetof(struct my_resource_table, devmem11),
        offsetof(struct my_resource_table, devmem12),
        offsetof(struct my_resource_table, devmem13),
        offsetof(struct my_resource_table, devmem14),
    },

    /* rpmsg vdev entry */
    {
        TYPE_VDEV, VIRTIO_ID_RPMSG, 0,
        RPMSG_DSP_C0_FEATURES, 0, 0, 0, 2, { 0, 0 },
        /* no config data */
    },
    /* the two vrings */
    { DSP_MEM_RPMSG_VRING0, 4096, DSP_RPMSG_VQ0_SIZE, 1, 0 },
    { DSP_MEM_RPMSG_VRING1, 4096, DSP_RPMSG_VQ1_SIZE, 2, 0 },

    {
        TYPE_CARVEOUT,
        DSP_MEM_TEXT, 0,
        DSP_MEM_TEXT_SIZE, 0, 0, "DSP_MEM_TEXT",
    },

    {
        TYPE_CARVEOUT,
        DSP_MEM_DATA, 0,
        DSP_MEM_DATA_SIZE, 0, 0, "DSP_MEM_DATA",
    },

    {
        TYPE_CARVEOUT,
        DSP_MEM_HEAP, 0,
        DSP_MEM_HEAP_SIZE, 0, 0, "DSP_MEM_HEAP",
    },

    {
        TYPE_CARVEOUT,
        DSP_MEM_IPC_DATA, 0,
        DSP_MEM_IPC_DATA_SIZE, 0, 0, "DSP_MEM_IPC_DATA",
    },

    {
        TYPE_TRACE, TRACEBUFADDR, 0x8000, 0, "trace:dsp",
    },

    {
        TYPE_DEVMEM,
       DSP_MEM_IPC_VRING, PHYS_MEM_IPC_VRING,
       DSP_MEM_IPC_VRING_SIZE, 0, 0, "DSP_MEM_IPC_VRING",
    },

    {
        TYPE_DEVMEM,
        DSP_MEM_IOBUFS, PHYS_MEM_IOBUFS,
        DSP_MEM_IOBUFS_SIZE, 0, 0, "DSP_MEM_IOBUFS",
    },

    {
        TYPE_DEVMEM,
        DSP_TILER_MODE_0_1, L3_TILER_MODE_0_1,
        SZ_256M, 0, 0, "DSP_TILER_MODE_0_1",
    },

    {
        TYPE_DEVMEM,
        DSP_TILER_MODE_2, L3_TILER_MODE_2,
        SZ_128M, 0, 0, "DSP_TILER_MODE_2",
    },

    {
        TYPE_DEVMEM,
        DSP_TILER_MODE_3, L3_TILER_MODE_3,
        SZ_128M, 0, 0, "DSP_TILER_MODE_3",
    },

    {
        TYPE_DEVMEM,
        DSP_PERIPHERAL_L4CFG, L4_PERIPHERAL_L4CFG,
        SZ_16M, 0, 0, "DSP_PERIPHERAL_L4CFG",
    },

    {
        TYPE_DEVMEM,
        DSP_PERIPHERAL_L4PER1, L4_PERIPHERAL_L4PER1,
        SZ_2M, 0, 0, "DSP_PERIPHERAL_L4PER1",
    },

    {
        TYPE_DEVMEM,
        DSP_PERIPHERAL_L4PER2, L4_PERIPHERAL_L4PER2,
        SZ_4M, 0, 0, "DSP_PERIPHERAL_L4PER2",
    },

    {
        TYPE_DEVMEM,
        DSP_PERIPHERAL_L4PER3, L4_PERIPHERAL_L4PER3,
        SZ_8M, 0, 0, "DSP_PERIPHERAL_L4PER3",
    },

    {
        TYPE_DEVMEM,
        DSP_PERIPHERAL_L4EMU, L4_PERIPHERAL_L4EMU,
        SZ_16M, 0, 0, "DSP_PERIPHERAL_L4EMU",
    },

    {
        TYPE_DEVMEM,
        DSP_PERIPHERAL_DMM, L3_PERIPHERAL_DMM,
        SZ_1M, 0, 0, "DSP_PERIPHERAL_DMM",
    },

    {
        TYPE_DEVMEM,
        DSP_PERIPHERAL_EDMA, L3_PERIPHERAL_EDMA,
        SZ_1M*3, 0, 0, "DSP_PERIPHERAL_EDMA",
    },
    {
        TYPE_DEVMEM,
        DSP_DDR_DATA, L3_DDR_DATA,
        SZ_1M, 0, 0, "DSP_DDR_DATA",
    },

    {
        TYPE_DEVMEM,
        DSP_CMEM_IOBUFS, PHYS_CMEM_IOBUFS,
        DSP_CMEM_IOBUFS_SIZE, 0, 0, "DSP_CMEM_IOBUFS",
    },

    {
         TYPE_DEVMEM,
         DSP_MCASP2_DATA, L3_MCASP2_DATA,
         SZ_1M*8, 0, 0, "DSP_MCASP2_DATA",
    },
};

#endif /* _RSC_TABLE_VAYU_DSP_H_ */

    

    


    

    DSP_MEM_TEXT is overlapping with ipu2_cma!!!
    

    The IPU2 program cannot execute, but normal execution of the DSP program.
    

    Normal execution of memtester, and audio file is normal on arm side.Why?
    

    

    

    I just modified the config.bld file and the rsc_table_vayu_dsp.c file, the start address was 0x9c000000, normal execution of the DSP program, but the memory data be changed.
    

    config.bld file
    

    EXT_CODE: {
        name: "EXT_CODE",
        base: 0x9c000000,
        len:  0x00100000,
        space: "code",
        access: "RWX"
    },
    EXT_DATA: {
        name: "EXT_DATA",
        base: 0x9c100000,
        len:  0x00500000,
        space: "data",
        access: "RW"
    },
    EXT_HEAP: {
        name: "EXT_HEAP",
        base: 0x9c600000,
        len:  0x00300000,
        space: "data",
        access: "RW"
    },
    

    rsc_table_vayu_dsp.c file
    

    #define DSP_MEM_TEXT            0x9c000000
/* Co-locate alongside TILER region for easier flushing */
#define DSP_MEM_IOBUFS          0x80000000
#define DSP_MEM_DATA            0x9c100000
#define DSP_MEM_HEAP            0x9c600000
    

    

    I don't understand that what is the correct address.
    

    

    regards
    

    June
    

    
			
    

		
		
		
		
	
    
	
    
		
    
			
		
    
	
    

	            
                	
	
    
				
		                
                
                
                
                
                
                
        		
		
				
    
			
		
    
		
		 
		
		
     
    
	
    

    
			
    
			
    
		
    

		
    
	
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													0
							
			
				
									
							
						
				
			
			
			
												
						in reply to jian35385
					
									
    
	
    
	                                    
                      
    
                        
                          Prodigy
                        150 points
                      
    
                          
                   		
		
    
					
    Jian, Tony,
    

    I modified the .dts file, added a reserved-memory
    

    dsp1_res@95000000 {
    reg = <0x0 0x95000000 0x0 0x800000>;
    no-map;
    status = "okay";
};
    

    

    modified the config.bld file
    

        EXT_CODE: {
        name: "EXT_CODE",
        base: 0x95000000,
        len:  0x00100000,
        space: "code",
        access: "RWX"
    },
    EXT_DATA: {
        name: "EXT_DATA",
        base: 0x95100000,
        len:  0x00400000,
        space: "data",
        access: "RW"
    },
    EXT_HEAP: {
        name: "EXT_HEAP",
        base: 0x95500000,
        len:  0x00300000,
        space: "data",
        access: "RW"
    },
    

    modified the rsc_table_vayu_dsp.c file
    

    #define DSP_MEM_TEXT            0x95000000
/* Co-locate alongside TILER region for easier flushing */
#define DSP_MEM_IOBUFS          0x80000000
#define DSP_MEM_DATA            0x95100000
#define DSP_MEM_HEAP            0x95500000

#define DSP_MEM_IPC_DATA        0x9F000000
#define DSP_MEM_IPC_VRING       0x99000000
#define DSP_MEM_RPMSG_VRING0    0x99000000
#define DSP_MEM_RPMSG_VRING1    0x99004000
#define DSP_MEM_VRING_BUFS0     0x99040000
#define DSP_MEM_VRING_BUFS1     0x99080000

#define DSP_PERIPHERAL_EDMA     0x43300000
#define L3_PERIPHERAL_EDMA      0x43300000
#define DSP_MCASP1_DATA         0x45800000
#define L3_MCASP1_DATA          0x45800000

#define DSP_MCASP2_DATA         0x45c00000
#define L3_MCASP2_DATA          0x45c00000

#define DSP_DDR_DATA            0x9B000000
#define L3_DDR_DATA             0x9B000000

#define DSP_MEM_IPC_VRING_SIZE  SZ_1M
#define DSP_MEM_IPC_DATA_SIZE   SZ_1M
#define DSP_MEM_TEXT_SIZE       SZ_1M
#define DSP_MEM_DATA_SIZE       (SZ_1M * 4)
#define DSP_MEM_HEAP_SIZE       (SZ_1M * 3)
#define DSP_MEM_IOBUFS_SIZE     (SZ_1M * 90)
    

    

    Normal execution of the DSP program, and the memory data will not be changed.
    

    complete files
    

    1106.am570x-mid.dts.txt
    

    



    
    
    
        Fullscreen
        6177.config.bld.txt
        Download
    
    
    
    /*
 * Copyright (c) 2013-2015, Texas Instruments Incorporated
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * *  Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 *
 * *  Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 *
 * *  Neither the name of Texas Instruments Incorporated nor the names of
 *    its contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */

/*
 *  ======== config.bld ========
 *
 */
var Build = xdc.useModule('xdc.bld.BuildEnvironment');

/*  Memory Map for ti.platforms.evmDRA7XX:dsp1 and ti.platforms.evmDRA7XX:dsp2
 *
 *  --- External Memory ---
 *  Virtual     Physical        Size            Comment
 *  ------------------------------------------------------------------------
 *  9500_4000   ????_????    10_0000  (  ~1 MB) EXT_CODE
 *  9510_0000   ????_????    10_0000  (   1 MB) EXT_DATA
 *  9520_0000   ????_????    30_0000  (   3 MB) EXT_HEAP
 *  9F00_0000   9F00_0000     6_0000  ( 384 kB) TRACE_BUF
 *  9F06_0000   9F06_0000     1_0000  (  64 kB) EXC_DATA
 *  9F07_0000   9F07_0000     2_0000  ( 128 kB) PM_DATA (Power mgmt)
 */
var evmDRA7XX_ExtMemMapDsp = {
    EXT_CODE: {
        name: "EXT_CODE",
        base: 0x95000000,
        len:  0x00100000,
        space: "code",
        access: "RWX"
    },
    EXT_DATA: {
        name: "EXT_DATA",
        base: 0x95100000,
        len:  0x00400000,
        space: "data",
        access: "RW"
    },
    EXT_HEAP: {
        name: "EXT_HEAP",
        base: 0x95500000,
        len:  0x00300000,
        space: "data",
        access: "RW"
    },
    TRACE_BUF: {
        name: "TRACE_BUF",
        base: 0x9F000000,
        len:  0x00060000,
        space: "data",
        access: "RW"
    },
    EXC_DATA: {
        name: "EXC_DATA",
        base: 0x9F060000,
        len:  0x00010000,
        space: "data",
        access: "RW"
    },
    PM_DATA: {
        name: "PM_DATA",
        base: 0x9F070000,
        len:  0x00020000,
        space: "data",
        access: "RWX"  /* should this have execute perm? */
    },
};

Build.platformTable["ti.platforms.evmDRA7XX:dsp1"] = {
    externalMemoryMap: [
        [ "EXT_CODE", evmDRA7XX_ExtMemMapDsp.EXT_CODE ],
        [ "EXT_DATA", evmDRA7XX_ExtMemMapDsp.EXT_DATA ],
        [ "EXT_HEAP", evmDRA7XX_ExtMemMapDsp.EXT_HEAP ],
        [ "TRACE_BUF", evmDRA7XX_ExtMemMapDsp.TRACE_BUF ],
        [ "EXC_DATA", evmDRA7XX_ExtMemMapDsp.EXC_DATA ],
        [ "PM_DATA", evmDRA7XX_ExtMemMapDsp.PM_DATA ],
    ],
    codeMemory: "EXT_CODE",
    dataMemory: "EXT_DATA",
    stackMemory: "EXT_DATA",
};
Build.platformTable["ti.platforms.evmDRA7XX:dsp2"] =
	Build.platformTable["ti.platforms.evmDRA7XX:dsp1"];



/*  Memory Map for ti.platforms.evmDRA7XX:ipu2
 *
 *  --- External Memory ---
 *  Virtual     Physical        Size            Comment
 *  ------------------------------------------------------------------------
 *  0000_4000   ????_????    5F_C000  (  ~6 MB) EXT_CODE
 *  8000_0000   ????_????    60_0000  (   6 MB) EXT_DATA
 *  8060_0000   ????_????   960_0000  (  86 MB) EXT_HEAP
 *  9F00_0000   9F00_0000     6_0000  ( 384 kB) TRACE_BUF
 *  9F06_0000   9F06_0000     1_0000  (  64 kB) EXC_DATA
 *  9F07_0000   9F07_0000     2_0000  ( 128 kB) PM_DATA (Power mgmt)
 */
var evmDRA7XX_ExtMemMapIpu2 = {
    EXT_CODE: {
        name: "EXT_CODE",
        base: 0x00004000,
        len:  0x005FC000,
        space: "code",
        access: "RWX"
    },
    EXT_DATA: {
        name: "EXT_DATA",
        base: 0x80000000,
        len:  0x00600000,
        space: "data",
        access: "RW"
    },
    EXT_HEAP: {
        name: "EXT_HEAP",
        base: 0x80600000,
        len:  0x09600000,
        space: "data",
        access: "RW"
    },
    TRACE_BUF: {
        name: "TRACE_BUF",
        base: 0x9F000000,
        len:  0x00060000,
        space: "data",
        access: "RW"
    },
    EXC_DATA: {
        name: "EXC_DATA",
        base: 0x9F060000,
        len:  0x00010000,
        space: "data",
        access: "RW"
    },
    PM_DATA: {
        name: "PM_DATA",
        base: 0x9F070000,
        len:  0x00020000,
        space: "data",
        access: "RWX"  /* should this have execute perm? */
    }
};

Build.platformTable["ti.platforms.evmDRA7XX:ipu2"] = {
    externalMemoryMap: [
        [ "EXT_CODE", evmDRA7XX_ExtMemMapIpu2.EXT_CODE ],
        [ "EXT_DATA", evmDRA7XX_ExtMemMapIpu2.EXT_DATA ],
        [ "EXT_HEAP", evmDRA7XX_ExtMemMapIpu2.EXT_HEAP ],
        [ "TRACE_BUF", evmDRA7XX_ExtMemMapIpu2.TRACE_BUF ],
        [ "EXC_DATA", evmDRA7XX_ExtMemMapIpu2.EXC_DATA ],
        [ "PM_DATA", evmDRA7XX_ExtMemMapIpu2.PM_DATA ]
    ],
    codeMemory: "EXT_CODE",
    dataMemory: "EXT_DATA",
    stackMemory: "EXT_DATA",
};

/*  Memory Map for ti.platforms.evmDRA7XX:ipu1
 *
 *  --- External Memory ---
 *  Virtual     Physical        Size            Comment
 *  ------------------------------------------------------------------------
 *  0000_4000   ????_????     F_C000  (  ~1 MB) EXT_CODE
 *  8000_0000   ????_????    20_0000  (   2 MB) EXT_DATA
 *  8020_0000   ????_????    30_0000  (   3 MB) EXT_HEAP
 *  9F00_0000   9F00_0000     6_0000  ( 384 kB) TRACE_BUF
 *  9F06_0000   9F06_0000     1_0000  (  64 kB) EXC_DATA
 *  9F07_0000   9F07_0000     2_0000  ( 128 kB) PM_DATA (Power mgmt)
 */
var evmDRA7XX_ExtMemMapIpu1 = {
    EXT_CODE: {
        name: "EXT_CODE",
        base: 0x00004000,
        len:  0x000FC000,
        space: "code",
        access: "RWX"
    },
    EXT_DATA: {
        name: "EXT_DATA",
        base: 0x80000000,
        len:  0x00200000,
        space: "data",
        access: "RW"
    },
    EXT_HEAP: {
        name: "EXT_HEAP",
        base: 0x80200000,
        len:  0x00300000,
        space: "data",
        access: "RW"
    },
    TRACE_BUF: {
        name: "TRACE_BUF",
        base: 0x9F000000,
        len:  0x00060000,
        space: "data",
        access: "RW"
    },
    EXC_DATA: {
        name: "EXC_DATA",
        base: 0x9F060000,
        len:  0x00010000,
        space: "data",
        access: "RW"
    },
    PM_DATA: {
        name: "PM_DATA",
        base: 0x9F070000,
        len:  0x00020000,
        space: "data",
        access: "RWX"  /* should this have execute perm? */
    }
};

Build.platformTable["ti.platforms.evmDRA7XX:ipu1"] = {
    externalMemoryMap: [
        [ "EXT_CODE", evmDRA7XX_ExtMemMapIpu1.EXT_CODE ],
        [ "EXT_DATA", evmDRA7XX_ExtMemMapIpu1.EXT_DATA ],
        [ "EXT_HEAP", evmDRA7XX_ExtMemMapIpu1.EXT_HEAP ],
        [ "TRACE_BUF", evmDRA7XX_ExtMemMapIpu1.TRACE_BUF ],
        [ "EXC_DATA", evmDRA7XX_ExtMemMapIpu1.EXC_DATA ],
        [ "PM_DATA", evmDRA7XX_ExtMemMapIpu1.PM_DATA ]
    ],
    codeMemory: "EXT_CODE",
    dataMemory: "EXT_DATA",
    stackMemory: "EXT_DATA",
};

    

    


    

    



    
    
    
        Fullscreen
        3716.rsc_table_vayu_dsp.c.txt
        Download
    
    
    
    /*
 * Copyright (c) 2012-2014, Texas Instruments Incorporated
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * *  Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 *
 * *  Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 *
 * *  Neither the name of Texas Instruments Incorporated nor the names of
 *    its contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */

/*
 *  ======== rsc_table_vayu_dsp.h ========
 *
 *  Define the resource table entries for all DSP cores. This will be
 *  incorporated into corresponding base images, and used by the remoteproc
 *  on the host-side to allocated/reserve resources.
 *
 */

#ifndef _RSC_TABLE_VAYU_DSP_H_
#define _RSC_TABLE_VAYU_DSP_H_

#include "rsc_types.h"

/* DSP Memory Map */
#define L4_DRA7XX_BASE          0x4A000000

#define L4_PERIPHERAL_L4CFG     (L4_DRA7XX_BASE)
#define DSP_PERIPHERAL_L4CFG    0x4A000000

#define L4_PERIPHERAL_L4PER1    0x48000000
#define DSP_PERIPHERAL_L4PER1   0x48000000

#define L4_PERIPHERAL_L4PER2    0x48400000
#define DSP_PERIPHERAL_L4PER2   0x48400000

#define L4_PERIPHERAL_L4PER3    0x48800000
#define DSP_PERIPHERAL_L4PER3   0x48800000

#define L4_PERIPHERAL_L4EMU     0x54000000
#define DSP_PERIPHERAL_L4EMU    0x54000000

#define L3_PERIPHERAL_DMM       0x4E000000
#define DSP_PERIPHERAL_DMM      0x4E000000

#define L3_TILER_MODE_0_1       0x60000000
#define DSP_TILER_MODE_0_1      0x60000000

#define L3_TILER_MODE_2         0x70000000
#define DSP_TILER_MODE_2        0x70000000

#define L3_TILER_MODE_3         0x78000000
#define DSP_TILER_MODE_3        0x78000000

#define DSP_MEM_TEXT            0x95000000
/* Co-locate alongside TILER region for easier flushing */
#define DSP_MEM_IOBUFS          0x80000000
#define DSP_MEM_DATA            0x95100000
#define DSP_MEM_HEAP            0x95500000

#define DSP_MEM_IPC_DATA        0x9F000000
#define DSP_MEM_IPC_VRING       0x99000000
#define DSP_MEM_RPMSG_VRING0    0x99000000
#define DSP_MEM_RPMSG_VRING1    0x99004000
#define DSP_MEM_VRING_BUFS0     0x99040000
#define DSP_MEM_VRING_BUFS1     0x99080000

#define DSP_PERIPHERAL_EDMA     0x43300000
#define L3_PERIPHERAL_EDMA      0x43300000
#define DSP_MCASP1_DATA         0x45800000
#define L3_MCASP1_DATA          0x45800000

#define DSP_MCASP2_DATA         0x45c00000
#define L3_MCASP2_DATA          0x45c00000

#define DSP_DDR_DATA            0x9B000000
#define L3_DDR_DATA             0x9B000000

#define DSP_MEM_IPC_VRING_SIZE  SZ_1M
#define DSP_MEM_IPC_DATA_SIZE   SZ_1M
#define DSP_MEM_TEXT_SIZE       SZ_1M
#define DSP_MEM_DATA_SIZE       (SZ_1M * 4)
#define DSP_MEM_HEAP_SIZE       (SZ_1M * 3)
#define DSP_MEM_IOBUFS_SIZE     (SZ_1M * 90)


/* NOTE: Make sure this matches what is configured in the linux device tree */
#define DSP_CMEM_IOBUFS 0xA0000000
#define PHYS_CMEM_IOBUFS 0xA0000000
#define DSP_CMEM_IOBUFS_SIZE (SZ_1M * 192)
/*
 * Assign fixed RAM addresses to facilitate a fixed MMU table.
 */

//BWC
#define VAYU_DSP_1

/* See CMA BASE addresses in Linux side: arch/arm/mach-omap2/remoteproc.c */
#if defined (VAYU_DSP_1)
#define PHYS_MEM_IPC_VRING      0x99000000
#elif defined (VAYU_DSP_2)
#define PHYS_MEM_IPC_VRING      0x9F000000
#endif

/* Need to be identical to that of IPU */
#define PHYS_MEM_IOBUFS         0xBA300000

/*
 * Sizes of the virtqueues (expressed in number of buffers supported,
 * and must be power of 2)
 */
#define DSP_RPMSG_VQ0_SIZE      256
#define DSP_RPMSG_VQ1_SIZE      256

/* flip up bits whose indices represent features we support */
#define RPMSG_DSP_C0_FEATURES         1

struct my_resource_table {
    struct resource_table base;

    UInt32 offset[21];  /* Should match 'num' in actual definition */

    /* rpmsg vdev entry */
    struct fw_rsc_vdev rpmsg_vdev;
    struct fw_rsc_vdev_vring rpmsg_vring0;
    struct fw_rsc_vdev_vring rpmsg_vring1;

    /* text carveout entry */
    struct fw_rsc_carveout text_cout;

    /* data carveout entry */
    struct fw_rsc_carveout data_cout;

    /* heap carveout entry */
    struct fw_rsc_carveout heap_cout;

    /* ipcdata carveout entry */
    struct fw_rsc_carveout ipcdata_cout;

    /* trace entry */
    struct fw_rsc_trace trace;

    /* devmem entry */
    struct fw_rsc_devmem devmem0;

    /* devmem entry */
    struct fw_rsc_devmem devmem1;

    /* devmem entry */
    struct fw_rsc_devmem devmem2;

    /* devmem entry */
    struct fw_rsc_devmem devmem3;

    /* devmem entry */
    struct fw_rsc_devmem devmem4;

    /* devmem entry */
    struct fw_rsc_devmem devmem5;

    /* devmem entry */
    struct fw_rsc_devmem devmem6;

    /* devmem entry */
    struct fw_rsc_devmem devmem7;

    /* devmem entry */
    struct fw_rsc_devmem devmem8;

    /* devmem entry */
    struct fw_rsc_devmem devmem9;

    /* devmem entry */
    struct fw_rsc_devmem devmem10;
    /* devmem entry */
    struct fw_rsc_devmem devmem11;

    /* devmem entry */
    struct fw_rsc_devmem devmem12;
    /* devmem entry */
        struct fw_rsc_devmem devmem13;
        /* devmem entry */
            struct fw_rsc_devmem devmem14;
};

//BWC added extern declaration
extern char ti_trace_SysMin_Module_State_0_outbuf__A;
#define TRACEBUFADDR (UInt32)&ti_trace_SysMin_Module_State_0_outbuf__A

#pragma DATA_SECTION(ti_ipc_remoteproc_ResourceTable, ".resource_table")
#pragma DATA_ALIGN(ti_ipc_remoteproc_ResourceTable, 4096)

struct my_resource_table ti_ipc_remoteproc_ResourceTable = {
    1,      /* we're the first version that implements this */
    21,     /* number of entries in the table */
    0, 0,   /* reserved, must be zero */
    /* offsets to entries */
    {
        offsetof(struct my_resource_table, rpmsg_vdev),
        offsetof(struct my_resource_table, text_cout),
        offsetof(struct my_resource_table, data_cout),
        offsetof(struct my_resource_table, heap_cout),
        offsetof(struct my_resource_table, ipcdata_cout),
        offsetof(struct my_resource_table, trace),
        offsetof(struct my_resource_table, devmem0),
        offsetof(struct my_resource_table, devmem1),
        offsetof(struct my_resource_table, devmem2),
        offsetof(struct my_resource_table, devmem3),
        offsetof(struct my_resource_table, devmem4),
        offsetof(struct my_resource_table, devmem5),
        offsetof(struct my_resource_table, devmem6),
        offsetof(struct my_resource_table, devmem7),
        offsetof(struct my_resource_table, devmem8),
        offsetof(struct my_resource_table, devmem9),
        offsetof(struct my_resource_table, devmem10),
        offsetof(struct my_resource_table, devmem11),
        offsetof(struct my_resource_table, devmem12),
        offsetof(struct my_resource_table, devmem13),
        offsetof(struct my_resource_table, devmem14),
    },

    /* rpmsg vdev entry */
    {
        TYPE_VDEV, VIRTIO_ID_RPMSG, 0,
        RPMSG_DSP_C0_FEATURES, 0, 0, 0, 2, { 0, 0 },
        /* no config data */
    },
    /* the two vrings */
    { DSP_MEM_RPMSG_VRING0, 4096, DSP_RPMSG_VQ0_SIZE, 1, 0 },
    { DSP_MEM_RPMSG_VRING1, 4096, DSP_RPMSG_VQ1_SIZE, 2, 0 },

    {
        TYPE_CARVEOUT,
        DSP_MEM_TEXT, 0,
        DSP_MEM_TEXT_SIZE, 0, 0, "DSP_MEM_TEXT",
    },

    {
        TYPE_CARVEOUT,
        DSP_MEM_DATA, 0,
        DSP_MEM_DATA_SIZE, 0, 0, "DSP_MEM_DATA",
    },

    {
        TYPE_CARVEOUT,
        DSP_MEM_HEAP, 0,
        DSP_MEM_HEAP_SIZE, 0, 0, "DSP_MEM_HEAP",
    },

    {
        TYPE_CARVEOUT,
        DSP_MEM_IPC_DATA, 0,
        DSP_MEM_IPC_DATA_SIZE, 0, 0, "DSP_MEM_IPC_DATA",
    },

    {
        TYPE_TRACE, TRACEBUFADDR, 0x8000, 0, "trace:dsp",
    },

    {
        TYPE_DEVMEM,
       DSP_MEM_IPC_VRING, PHYS_MEM_IPC_VRING,
       DSP_MEM_IPC_VRING_SIZE, 0, 0, "DSP_MEM_IPC_VRING",
    },

    {
        TYPE_DEVMEM,
        DSP_MEM_IOBUFS, PHYS_MEM_IOBUFS,
        DSP_MEM_IOBUFS_SIZE, 0, 0, "DSP_MEM_IOBUFS",
    },

    {
        TYPE_DEVMEM,
        DSP_TILER_MODE_0_1, L3_TILER_MODE_0_1,
        SZ_256M, 0, 0, "DSP_TILER_MODE_0_1",
    },

    {
        TYPE_DEVMEM,
        DSP_TILER_MODE_2, L3_TILER_MODE_2,
        SZ_128M, 0, 0, "DSP_TILER_MODE_2",
    },

    {
        TYPE_DEVMEM,
        DSP_TILER_MODE_3, L3_TILER_MODE_3,
        SZ_128M, 0, 0, "DSP_TILER_MODE_3",
    },

    {
        TYPE_DEVMEM,
        DSP_PERIPHERAL_L4CFG, L4_PERIPHERAL_L4CFG,
        SZ_16M, 0, 0, "DSP_PERIPHERAL_L4CFG",
    },

    {
        TYPE_DEVMEM,
        DSP_PERIPHERAL_L4PER1, L4_PERIPHERAL_L4PER1,
        SZ_2M, 0, 0, "DSP_PERIPHERAL_L4PER1",
    },

    {
        TYPE_DEVMEM,
        DSP_PERIPHERAL_L4PER2, L4_PERIPHERAL_L4PER2,
        SZ_4M, 0, 0, "DSP_PERIPHERAL_L4PER2",
    },

    {
        TYPE_DEVMEM,
        DSP_PERIPHERAL_L4PER3, L4_PERIPHERAL_L4PER3,
        SZ_8M, 0, 0, "DSP_PERIPHERAL_L4PER3",
    },

    {
        TYPE_DEVMEM,
        DSP_PERIPHERAL_L4EMU, L4_PERIPHERAL_L4EMU,
        SZ_16M, 0, 0, "DSP_PERIPHERAL_L4EMU",
    },

    {
        TYPE_DEVMEM,
        DSP_PERIPHERAL_DMM, L3_PERIPHERAL_DMM,
        SZ_1M, 0, 0, "DSP_PERIPHERAL_DMM",
    },

    {
        TYPE_DEVMEM,
        DSP_PERIPHERAL_EDMA, L3_PERIPHERAL_EDMA,
        SZ_1M*3, 0, 0, "DSP_PERIPHERAL_EDMA",
    },
    {
        TYPE_DEVMEM,
        DSP_DDR_DATA, L3_DDR_DATA,
        SZ_1M, 0, 0, "DSP_DDR_DATA",
    },

    {
        TYPE_DEVMEM,
        DSP_CMEM_IOBUFS, PHYS_CMEM_IOBUFS,
        DSP_CMEM_IOBUFS_SIZE, 0, 0, "DSP_CMEM_IOBUFS",
    },

    {
         TYPE_DEVMEM,
         DSP_MCASP2_DATA, L3_MCASP2_DATA,
         SZ_1M*8, 0, 0, "DSP_MCASP2_DATA",
    },
};

#endif /* _RSC_TABLE_VAYU_DSP_H_ */

    

    


    

    

    regards
    

    June
    
			
    

		
		
		
		
	
    
	
    
		
    
			
		
    
	
    

	            
                	
	
    
				
		                
                
                
                
                
                
                
        		
		
				
    
			
		
    
		
		 
		
		
     
    
	
    

    
			
    
			
    
		
    

		
    
	
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													0
							
			
				
									
							
						
				
			
			
			
												
						in reply to user6342709
					
									
    
	
    
	                                    
                      
    
                        
                          TI__Mastermind
                        23125 points
                      
    
                          
                   		
		
    
					
    June, 
    

    I was distracted from another task until now. I noticed you made multiple experiments during the week, where in the 5/25 post, you had the following CMA carveout memory regions:
    

    0x95000000 - 0x95800000 (8MB), dsp1_res
    0x95800000 - 0x99000000 (56MB), ipu2_cma
    0x99000000 - 0x9D000000 (64MB), dsp1_cma
    0x9D000000 - 0x9F000000 (32MB), ipu1_cma
    

    Then I saw you put the DSP text, data and heap in the dsp1_res region. Is there a reason you did not put DSP memory in the dsp1_cma region?
    

    You mentioned
    

    " Normal execution of the DSP program, and the memory data will not be changed."
    

    Does that means the original issue of ARM data corruption is solved?
    

    sorry for the delay.
    

    Jian
    
			
    

		
		
		
		
	
    
	
    
		
    
			
		
    
	
    

	            
                 	
	
    
				
		                
                
                
                
                
                
                
        		
		
				
    
			
		
    
		
		 
		
		
     
    
	
    

    
			
    
			
    
		
    

		
    
	
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													0
							
			
				
									
							
						
				
			
			
			
												
						in reply to jian35385
					
									
    
	
    
	                                    
                      
    
                        
                          Prodigy
                        150 points
                      
    
                          
                   		
		
    
					
    Jian,
    

    I tried to put the DSP text, data and heap in the dsp1_cma region, the start address was 0x9c000000, but the issue of ARM data corruption still existed.
    

    So I created a CMA carveout memory region, and put the DSP text, data and heap in this region.
    

    0x95000000 - 0x95800000 (8MB), dsp1_res
    

    I tested again, the issue was solved.
    

    But I couldn't find the cause of the problem.
    

    Did you have any ideas?
    

    regards
    

    June
    

    
			
    

		
		
		
		
	
    
	
    
		
    
			
		
    
	
    

	            
                	
	
    
				
		                
                
                
                
                
                
                
        		
		
				
    
			
		
    
		
		 
		
		
     
    
	
    

    
			
    
			
    
		
    

		
    
	
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													0
							
			
				
									
							
						
				
			
			
			
												
						in reply to user6342709
					
									
    
	
    
	                                    
                      
    
                        
                          TI__Mastermind
                        23125 points
                      
    
                          
                   		
		
    
					
    June, 
    

    I was not able spot conflict in your memory partition via dts file and dsp memory map. So with the passing test with the dsp1_res memory case, can you send the linux memory map by: 
    

    cat /proc/iomem
    

     you sent one in the earlier post, but that one seems not the final dts. I am wondering something in Linux wrapped to DDR 0x9c000000. 
    

    Jian
    

    
			
    

		
		
		
		
	
    
	
    
		
    
			
		
    
	
    

	            
                 	
	
    
				
		                
                
                
                
                
                
                
        		
		
				
    
			
		
    
		
		 
		
		
     
    
	
    

    
			
    
			
    
		
    

		
    
	
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													0
							
			
				
									
							
						
				
			
			
			
												
						in reply to jian35385
					
									
    
	
    
	                                    
                      
    
                        
                          Prodigy
                        150 points
                      
    
                          
                   		
		
    
					
    Jian,
    

    1. Put the DSP text, data and heap in the dsp1_res region, the start address was 0x95000000.
    

    

    



    
    
    
        Fullscreen
        1050.log1.txt
        Download
    
    
    
    root@am57xx-evm:/lib/firmware# cat /proc/iomem 
40300000-4037ffff : 40300000.ocmcram
40800000-40847fff : l2ram
40d01000-40d010ff : /ocp/mmu@40d01000
40d02000-40d020ff : /ocp/mmu@40d02000
43300000-433fffff : edma3_cc
44000000-44ffffff : /ocp
45000000-45000fff : /ocp
48020000-4802001f : serial
48032000-4803207f : /ocp/timer@48032000
48034000-4803407f : /ocp/timer@48034000
48036000-4803607f : /ocp/timer@48036000
4803e000-4803e07f : /ocp/timer@4803e000
48051000-480511ff : /ocp/gpio@48051000
48053000-480531ff : /ocp/gpio@48053000
48055000-480551ff : /ocp/gpio@48055000
48057000-480571ff : /ocp/gpio@48057000
48059000-480591ff : /ocp/gpio@48059000
4805b000-4805b1ff : /ocp/gpio@4805b000
4805d000-4805d1ff : /ocp/gpio@4805d000
48060000-480600ff : /ocp/i2c@48060000
48070000-480700ff : /ocp/i2c@48070000
4807a000-4807a0ff : /ocp/i2c@4807a000
48086000-4808607f : /ocp/timer@48086000
48088000-4808807f : /ocp/timer@48088000
48090000-48091fff : /ocp/rng@48090000
48098100-480982ff : /ocp/spi@48098000
4809a100-4809a2ff : /ocp/spi@4809a000
4809c000-4809c3ff : /ocp/mmc@4809c000
480a5000-480a509f : /ocp/des@480a5000
480ad000-480ad3ff : /ocp/mmc@480ad000
480b4000-480b43ff : /ocp/mmc@480b4000
480d1000-480d13ff : /ocp/mmc@480d1000
48440200-4844027f : /ocp/epwmss@48440000/pwm@48440200
4844a000-4844ad1b : /ocp/padconf@4844a000
48484000-48484fff : /ocp/ethernet@48484000
48485000-484850ff : /ocp/ethernet@48484000/mdio@48485000
48485200-48487fff : /ocp/ethernet@48484000
48820000-4882007f : /ocp/timer@48820000
48822000-4882207f : /ocp/timer@48822000
48824000-4882407f : /ocp/timer@48824000
48826000-4882607f : /ocp/timer@48826000
48828000-4882807f : /ocp/timer@48828000
4882a000-4882a07f : /ocp/timer@4882a000
4882c000-4882c07f : /ocp/timer@4882c000
4882e000-4882e07f : /ocp/timer@4882e000
4883c000-4883c1ff : /ocp/mailbox@4883c000
4883e000-4883e1ff : /ocp/mailbox@4883e000
48840000-488401ff : /ocp/mailbox@48840000
48842000-488421ff : /ocp/mailbox@48842000
48880000-4888ffff : /ocp/omap_dwc3_1@48880000
48890000-48897fff : /ocp/omap_dwc3_1@48880000/usb@48890000
  48890000-48897fff : /ocp/omap_dwc3_1@48880000/usb@48890000
4889c100-488a6fff : /ocp/omap_dwc3_1@48880000/usb@48890000
488c0000-488cffff : /ocp/omap_dwc3_2@488c0000
488d0000-488d7fff : /ocp/omap_dwc3_2@488c0000/usb@488d0000
  488d0000-488d7fff : /ocp/omap_dwc3_2@488c0000/usb@488d0000
488dc100-488e6fff : /ocp/omap_dwc3_2@488c0000/usb@488d0000
48970000-48970113 : vip
48975500-489755d7 : parser0
48975700-48975717 : csc0
48975800-4897587f : sc0
48975a00-48975ad7 : parser1
48975c00-48975c17 : csc1
48975d00-48975d7f : sc1
489d0700-489d077f : sc
489d5700-489d5717 : csc
4a0021e0-4a0021eb : /ocp/bandgap@4a0021e0
4a00232c-4a002337 : /ocp/bandgap@4a0021e0
4a002380-4a0023ab : /ocp/bandgap@4a0021e0
4a0023c0-4a0023fb : /ocp/bandgap@4a0021e0
4a00246c-4a00246f : ldo-address
4a002470-4a002473 : ldo-address
4a002554-4a002557 : gmii-sel
4a002564-4a00256b : /ocp/bandgap@4a0021e0
4a002574-4a0025c3 : /ocp/bandgap@4a0021e0
4a002b78-4a002c73 : /ocp/l4@4a000000/scm@2000/dma-router@b78
4a002c78-4a002cf3 : /ocp/l4@4a000000/scm@2000/dma-router@c78
4a002e8c-4a002e8f : pinctrl-single
4a003400-4a003867 : pinctrl-single
4a056000-4a056fff : omap_dma_system.0
  4a056000-4a056fff : /ocp/dma-controller@4a056000
4a080000-4a08001f : /ocp/ocp2scp@4a080000
4a084000-4a0843ff : /ocp/ocp2scp@4a080000/phy@4a084000
4a084c00-4a084c3f : pll_ctrl
4a085000-4a0853ff : /ocp/ocp2scp@4a080000/phy@4a085000
4a090000-4a09001f : /ocp/ocp2scp@4a090000
4a096800-4a09683f : pll_ctrl
4ae07ddc-4ae07ddf : setup-address
4ae07de0-4ae07de3 : control-address
4ae07de4-4ae07de7 : setup-address
4ae07de8-4ae07deb : control-address
4ae07e20-4ae07e23 : control-address
4ae07e24-4ae07e27 : control-address
4ae07e30-4ae07e33 : setup-address
4ae07e34-4ae07e37 : setup-address
4ae0c154-4ae0c157 : ldo-address
4ae0c158-4ae0c15b : ldo-address
4ae10000-4ae101ff : /ocp/gpio@4ae10000
4ae14000-4ae1407f : /ocp/wdt@4ae14000
4ae20000-4ae2007f : /ocp/timer@4ae20000
4b101000-4b1012ff : /ocp/sham@53100000
4b200000-4b201fff : dram0
4b202000-4b203fff : dram1
4b210000-4b217fff : shrdram2
4b220000-4b221fff : intc
4b222000-4b2223ff : control
4b222400-4b2224ff : debug
4b224000-4b2243ff : control
4b224400-4b2244ff : debug
4b226000-4b227fff : cfg
4b22e000-4b22e31b : iep
4b232000-4b232057 : mii_rt
4b234000-4b236fff : iram
4b238000-4b23afff : iram
4b280000-4b281fff : dram0
4b282000-4b283fff : dram1
4b290000-4b297fff : shrdram2
4b2a0000-4b2a1fff : intc
4b2a2000-4b2a23ff : control
4b2a2400-4b2a24ff : debug
4b2a4000-4b2a43ff : control
4b2a4400-4b2a44ff : debug
4b2a6000-4b2a7fff : cfg
4b2ae000-4b2ae31b : iep
4b2b2000-4b2b2057 : mii_rt
4b2b4000-4b2b6fff : iram
4b2b8000-4b2bafff : iram
4b300000-4b3000ff : qspi_base
4b500000-4b50009f : /ocp/aes@4b500000
4b700000-4b70009f : /ocp/aes@4b700000
55020000-5502ffff : l2ram
55082000-550820ff : /ocp/mmu@55082000
58004054-58004057 : pll1_clkctrl
58004300-5800431f : pll1
58040000-580401ff : wp
58040200-5804027f : pll
58040300-5804037f : phy
58060000-58078fff : core
58820000-5882ffff : l2ram
58882000-588820ff : /ocp/mmu@58882000
80000000-94ffffff : System RAM
  80008000-80dfffff : Kernel code
  81000000-8109b1ef : Kernel data
95800000-9fffffff : System RAM
a0000000-abffffff : CMEM
ac000000-bfdfffff : System RAM
root@am57xx-evm:/lib/firmware# dmesg | grep -i cma
[    0.000000] Reserved memory: created CMA memory pool at 0x0000000095800000, size 56 MiB
[    0.000000] OF: reserved mem: initialized node ipu2_cma@95800000, compatible id shared-dma-pool
[    0.000000] Reserved memory: created CMA memory pool at 0x0000000099000000, size 64 MiB
[    0.000000] OF: reserved mem: initialized node dsp1_cma@99000000, compatible id shared-dma-pool
[    0.000000] Reserved memory: created CMA memory pool at 0x000000009d000000, size 32 MiB
[    0.000000] OF: reserved mem: initialized node ipu1_cma@9d000000, compatible id shared-dma-pool
[    0.000000] cma: Reserved 24 MiB at 0x00000000be400000
[    0.000000] Memory: 637456K/841728K available (8192K kernel code, 317K rwdata, 2472K rodata, 2048K init, 296K bss, 24048K reserved, 180224K cma-reserved, 235520K highmem)
[    7.756074] omap-rproc 58820000.ipu: assigned reserved memory node ipu1_cma@9d000000
[    7.945674] omap-rproc 55020000.ipu: assigned reserved memory node ipu2_cma@95800000
[    8.979277] omap-rproc 40800000.dsp: assigned reserved memory node dsp1_cma@99000000
root@am57xx-evm:/lib/firmware#
    

    


    

    

    2. Put the DSP text, data and heap in the dsp1_cma region, the start address was 0x9c000000.
    

    



    
    
    
        Fullscreen
        3051.log2.txt
        Download
    
    
    
    root@am57xx-evm:/lib/firmware# cat /proc/iomem    
40300000-4037ffff : 40300000.ocmcram
40800000-40847fff : l2ram
40d01000-40d010ff : /ocp/mmu@40d01000
40d02000-40d020ff : /ocp/mmu@40d02000
43300000-433fffff : edma3_cc
44000000-44ffffff : /ocp
45000000-45000fff : /ocp
48020000-4802001f : serial
48032000-4803207f : /ocp/timer@48032000
48034000-4803407f : /ocp/timer@48034000
48036000-4803607f : /ocp/timer@48036000
4803e000-4803e07f : /ocp/timer@4803e000
48051000-480511ff : /ocp/gpio@48051000
48053000-480531ff : /ocp/gpio@48053000
48055000-480551ff : /ocp/gpio@48055000
48057000-480571ff : /ocp/gpio@48057000
48059000-480591ff : /ocp/gpio@48059000
4805b000-4805b1ff : /ocp/gpio@4805b000
4805d000-4805d1ff : /ocp/gpio@4805d000
48060000-480600ff : /ocp/i2c@48060000
48070000-480700ff : /ocp/i2c@48070000
4807a000-4807a0ff : /ocp/i2c@4807a000
48086000-4808607f : /ocp/timer@48086000
48088000-4808807f : /ocp/timer@48088000
48090000-48091fff : /ocp/rng@48090000
48098100-480982ff : /ocp/spi@48098000
4809a100-4809a2ff : /ocp/spi@4809a000
4809c000-4809c3ff : /ocp/mmc@4809c000
480a5000-480a509f : /ocp/des@480a5000
480ad000-480ad3ff : /ocp/mmc@480ad000
480b4000-480b43ff : /ocp/mmc@480b4000
480d1000-480d13ff : /ocp/mmc@480d1000
48440200-4844027f : /ocp/epwmss@48440000/pwm@48440200
4844a000-4844ad1b : /ocp/padconf@4844a000
48484000-48484fff : /ocp/ethernet@48484000
48485000-484850ff : /ocp/ethernet@48484000/mdio@48485000
48485200-48487fff : /ocp/ethernet@48484000
48820000-4882007f : /ocp/timer@48820000
48822000-4882207f : /ocp/timer@48822000
48824000-4882407f : /ocp/timer@48824000
48826000-4882607f : /ocp/timer@48826000
48828000-4882807f : /ocp/timer@48828000
4882a000-4882a07f : /ocp/timer@4882a000
4882c000-4882c07f : /ocp/timer@4882c000
4882e000-4882e07f : /ocp/timer@4882e000
4883c000-4883c1ff : /ocp/mailbox@4883c000
4883e000-4883e1ff : /ocp/mailbox@4883e000
48840000-488401ff : /ocp/mailbox@48840000
48842000-488421ff : /ocp/mailbox@48842000
48880000-4888ffff : /ocp/omap_dwc3_1@48880000
48890000-48897fff : /ocp/omap_dwc3_1@48880000/usb@48890000
  48890000-48897fff : /ocp/omap_dwc3_1@48880000/usb@48890000
4889c100-488a6fff : /ocp/omap_dwc3_1@48880000/usb@48890000
488c0000-488cffff : /ocp/omap_dwc3_2@488c0000
488d0000-488d7fff : /ocp/omap_dwc3_2@488c0000/usb@488d0000
  488d0000-488d7fff : /ocp/omap_dwc3_2@488c0000/usb@488d0000
488dc100-488e6fff : /ocp/omap_dwc3_2@488c0000/usb@488d0000
48970000-48970113 : vip
48975500-489755d7 : parser0
48975700-48975717 : csc0
48975800-4897587f : sc0
48975a00-48975ad7 : parser1
48975c00-48975c17 : csc1
48975d00-48975d7f : sc1
489d0700-489d077f : sc
489d5700-489d5717 : csc
4a0021e0-4a0021eb : /ocp/bandgap@4a0021e0
4a00232c-4a002337 : /ocp/bandgap@4a0021e0
4a002380-4a0023ab : /ocp/bandgap@4a0021e0
4a0023c0-4a0023fb : /ocp/bandgap@4a0021e0
4a00246c-4a00246f : ldo-address
4a002470-4a002473 : ldo-address
4a002554-4a002557 : gmii-sel
4a002564-4a00256b : /ocp/bandgap@4a0021e0
4a002574-4a0025c3 : /ocp/bandgap@4a0021e0
4a002b78-4a002c73 : /ocp/l4@4a000000/scm@2000/dma-router@b78
4a002c78-4a002cf3 : /ocp/l4@4a000000/scm@2000/dma-router@c78
4a002e8c-4a002e8f : pinctrl-single
4a003400-4a003867 : pinctrl-single
4a056000-4a056fff : omap_dma_system.0
  4a056000-4a056fff : /ocp/dma-controller@4a056000
4a080000-4a08001f : /ocp/ocp2scp@4a080000
4a084000-4a0843ff : /ocp/ocp2scp@4a080000/phy@4a084000
4a084c00-4a084c3f : pll_ctrl
4a085000-4a0853ff : /ocp/ocp2scp@4a080000/phy@4a085000
4a090000-4a09001f : /ocp/ocp2scp@4a090000
4a096800-4a09683f : pll_ctrl
4ae07ddc-4ae07ddf : setup-address
4ae07de0-4ae07de3 : control-address
4ae07de4-4ae07de7 : setup-address
4ae07de8-4ae07deb : control-address
4ae07e20-4ae07e23 : control-address
4ae07e24-4ae07e27 : control-address
4ae07e30-4ae07e33 : setup-address
4ae07e34-4ae07e37 : setup-address
4ae0c154-4ae0c157 : ldo-address
4ae0c158-4ae0c15b : ldo-address
4ae10000-4ae101ff : /ocp/gpio@4ae10000
4ae14000-4ae1407f : /ocp/wdt@4ae14000
4ae20000-4ae2007f : /ocp/timer@4ae20000
4b101000-4b1012ff : /ocp/sham@53100000
4b200000-4b201fff : dram0
4b202000-4b203fff : dram1
4b210000-4b217fff : shrdram2
4b220000-4b221fff : intc
4b222000-4b2223ff : control
4b222400-4b2224ff : debug
4b224000-4b2243ff : control
4b224400-4b2244ff : debug
4b226000-4b227fff : cfg
4b22e000-4b22e31b : iep
4b232000-4b232057 : mii_rt
4b234000-4b236fff : iram
4b238000-4b23afff : iram
4b280000-4b281fff : dram0
4b282000-4b283fff : dram1
4b290000-4b297fff : shrdram2
4b2a0000-4b2a1fff : intc
4b2a2000-4b2a23ff : control
4b2a2400-4b2a24ff : debug
4b2a4000-4b2a43ff : control
4b2a4400-4b2a44ff : debug
4b2a6000-4b2a7fff : cfg
4b2ae000-4b2ae31b : iep
4b2b2000-4b2b2057 : mii_rt
4b2b4000-4b2b6fff : iram
4b2b8000-4b2bafff : iram
4b300000-4b3000ff : qspi_base
4b500000-4b50009f : /ocp/aes@4b500000
4b700000-4b70009f : /ocp/aes@4b700000
55020000-5502ffff : l2ram
55082000-550820ff : /ocp/mmu@55082000
58004054-58004057 : pll1_clkctrl
58004300-5800431f : pll1
58040000-580401ff : wp
58040200-5804027f : pll
58040300-5804037f : phy
58060000-58078fff : core
58820000-5882ffff : l2ram
58882000-588820ff : /ocp/mmu@58882000
80000000-9fffffff : System RAM
  80008000-80dfffff : Kernel code
  81000000-8109b1ef : Kernel data
a0000000-abffffff : CMEM
ac000000-bfdfffff : System RAM
root@am57xx-evm:/lib/firmware# dmesg | grep -i cma
[    0.000000] Reserved memory: created CMA memory pool at 0x0000000095800000, size 56 MiB
[    0.000000] OF: reserved mem: initialized node ipu2_cma@95800000, compatible id shared-dma-pool
[    0.000000] Reserved memory: created CMA memory pool at 0x0000000099000000, size 64 MiB
[    0.000000] OF: reserved mem: initialized node dsp1_cma@99000000, compatible id shared-dma-pool
[    0.000000] Reserved memory: created CMA memory pool at 0x000000009d000000, size 32 MiB
[    0.000000] OF: reserved mem: initialized node ipu1_cma@9d000000, compatible id shared-dma-pool
[    0.000000] cma: Reserved 24 MiB at 0x00000000be400000
[    0.000000] Memory: 645576K/849920K available (8192K kernel code, 317K rwdata, 2472K rodata, 2048K init, 296K bss, 24120K reserved, 180224K cma-reserved, 235520K highmem)
[    7.748444] omap-rproc 58820000.ipu: assigned reserved memory node ipu1_cma@9d000000
[    7.871753] omap-rproc 55020000.ipu: assigned reserved memory node ipu2_cma@95800000
[    8.030384] omap-rproc 40800000.dsp: assigned reserved memory node dsp1_cma@99000000
root@am57xx-evm:/lib/firmware# 

    

    


    

    The difference was System RAM.
    

     
    

    

    regards
    

    June
    
			
    

		
		
		
		
	
    
	
    
		
    
			
		
    
	
    

	            
                	
	
    
				
		                
                
                
                
                
                
                
        		
		
				
    
			
		
    
		
		 
		
		
     
    
	
    

    
			
    
			
    
		
    

		
    
	
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                          TI__Mastermind
                        23125 points
                      
    
                          
                   		
		
    
					
    June, 
    

    Thanks for the log files. For case #2, have you tried to change the dsp1_cma region as "no-map;" instead of "reusable;" and see if the test can pass?
    

    Also can you confirm if you are using any early-boot functions in your system? i.e., bringing up a core other than the A15/Linux ahead of Linux boot, as described:
    

    http://software-dl.ti.com/processor-sdk-linux/esd/docs/06_03_00_106/linux/Foundational_Components_IPC.html#ipc-for-am57xx
    

    From the descriptions, it sounds like DSP was attempting to be early-booted.
    

    Jian
    
			
    

		
		
		
		
	
    
	
    
		
    
			
		
    
	
    

	            
                 	
	
    
				
		                
                
                
                
                
                
                
        		
		
				
    
			
		
    
		
		 
		
		
     
    
	
    

    
			
    
			
    
		
    

		
    
	
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													0
							
			
				
									
							
						
				
			
			
			
												
						in reply to jian35385
					
									
    
	
    
	                                    
                      
    
                        
                          Prodigy
                        150 points
                      
    
                          
                   		
		
    
					
    Jian,
    

    

    "Put the DSP text, data and heap in the dsp1_cma region, the start address was 0x9c000000."
    

    

    I tried to change the dsp1_cma region as "no-map;" and tested again, the memory data will not be changed.
    

    0x9c000000 was a secure address in the dsp1_cma region.
    

    

    I looked at the documentation, but I didn't understand the reusable meaning.
    

    How to confirm the current working mode, typical boot or early boot?
    

    

    cat /sys/kernel/debug/remoteproc/remoteproc0/trace0
    

    



    
    
    
        Fullscreen
        3404.log.txt
        Download
    
    
    
    root@am57xx-evm:~# cat /sys/kernel/debug/remoteproc/remoteproc0/trace0 
[0][      0.000] Watchdog enabled: TimerBase = 0x68824000 SMP-Core = 0 Freq = 19200000
[0][      0.000] Watchdog enabled: TimerBase = 0x68826000 SMP-Core = 1 Freq = 19200000
[0][      0.000] Watchdog_restore registered as a resume callback
[0][      0.000] 18 Resource entries at 0x3000
[0][      0.000] IPU1 starting..
[0][      0.000] register_MxServer: -->
[0][      0.000] OMAPRPC: registered channel: rpc_example_2
[0][      0.000] OMAPRPC: Returning Object @800492c0
[0][      0.000] register_MxServer: <--, status=0
[0][      0.000] copyTask sample1:50: Entered...:
[1][      0.000] copyTask sample2:51: Entered...:
[0][      0.000] registering rpmsg-client-sample:sample1 service on 50 with HOST
[1][      0.000] registering rpmsg-client-sample:sample2 service on 51 with HOST
[0][      0.000] OmxSrvMgr: started on port: 60
[1][      0.000] OMAPRPC: connecting from local endpoint 101 to port 101
[0][      0.000] registering rpmsg-omx:rpmsg-omx3 service on 60 with HOST
[1][      0.000] registering rpmsg-rpc:rpc_example_2 service on 101 with HOST
[0][      0.001] OmxSrvMgr: Proc#2 sending BOOTINIT_DONE
[1][      0.001] OMAPRPC: started channel rpc_example_2 on port: 101
[0][      6.681] OMAPRPC: received msg type: 0 len: 8 from addr: 1024
[0][      6.682] OMAPRPC: channel info query - name rpc_example_2 fxns 8
[0][      6.682] OMAPRPC: Replying with msg type: 1 to addr: 1024  from: 101 len: 12
[0][      7.201] OMAPRPC: received msg type: 2 len: 216 from addr: 1024
[0][      7.202] OMAPRPC: function query of type 1
[0][      7.202] OMAPRPC: Replying with msg type: 3 to addr: 1024  from: 101 len: 216
[0][      7.288] OMAPRPC: received msg type: 2 len: 216 from addr: 1024
[0][      7.288] OMAPRPC: function query of type 1
[0][      7.288] OMAPRPC: Replying with msg type: 3 to addr: 1024  from: 101 len: 216
[0][      7.348] OMAPRPC: received msg type: 2 len: 216 from addr: 1024
[0][      7.348] OMAPRPC: function query of type 1
[0][      7.349] OMAPRPC: Replying with msg type: 3 to addr: 1024  from: 101 len: 216
[0][      7.505] OMAPRPC: received msg type: 2 len: 216 from addr: 1024
[0][      7.505] OMAPRPC: function query of type 1
[0][      7.506] OMAPRPC: Replying with msg type: 3 to addr: 1024  from: 101 len: 216
[0][      7.524] OMAPRPC: received msg type: 2 len: 216 from addr: 1024
[0][      7.524] OMAPRPC: function query of type 1
[0][      7.524] OMAPRPC: Replying with msg type: 3 to addr: 1024  from: 101 len: 216
[0][      7.524] OMAPRPC: received msg type: 2 len: 216 from addr: 1024
[0][      7.525] OMAPRPC: function query of type 1
[0][      7.525] OMAPRPC: Replying with msg type: 3 to addr: 1024  from: 101 len: 216
[0][      7.525] OMAPRPC: received msg type: 2 len: 216 from addr: 1024
[0][      7.525] OMAPRPC: function query of type 1
[0][      7.525] OMAPRPC: Replying with msg type: 3 to addr: 1024  from: 101 len: 216
[0][      7.526] OMAPRPC: received msg type: 2 len: 216 from addr: 1024
[0][      7.526] OMAPRPC: function query of type 1
[0][      7.526] OMAPRPC: Replying with msg type: 3 to addr: 1024  from: 101 len: 216
root@am57xx-evm:~# 
    

    


    

    

    regards
    

    June
    

    

    
			
    

		
		
		
		
	
    
	
    
		
    
			
		
    
	
    

	            
                	
	
    
				
		                
                
                
                
                
                
                
        		
		
				
    
			
		
    
		
		 
		
		
     
    
	
    

    
			
    
			
    
		
    

		
    
	
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													0
							
			
				
									
							
						
				
			
			
			
												
						in reply to user6342709
					
									
    
	
    
	                                    
                      
    
                        
                          TI__Mastermind
                        23125 points
                      
    
                          
                   		
		
    
					
    June, 
    

    I am waiting on some pointer to CMA attributes definition. In the mean time, can you let me know how which method you used to load DSP code along with Linux?
    

    regards
    

    Jian
    
			
    

		
		
		
		
	
    
	
    
		
    
			
		
    
	
    

	            
                 	
	
    
				
		                
                
                
                
                
                
                
        		
		
				
    
			
		
    
		
		 
		
		
     
    
	
    

    
			
    
			
    
		
    

		
    
	
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													0
							
			
				
									
							
						
				
			
			
			
												
						in reply to jian35385
					
									
    
	
    
	                                    
                      
    
                        
                          Prodigy
                        10 points
                      
    
                          
                   		
		
    
					
    jian,
    

    After the system starts, the relevant driver modules are loaded, and then the driver finds the DSP firmware in the file system and transmits it to the DSP.
    

    The DSP firmware is placed in the directory of /lib/fireware, and the link to modify the DSP firmware is as follows.
    

    cd /lib/firmware
rm dra7-dsp1-fw.xe66
ln -s Audio_Capture_Dsp.out dra7-dsp1-fw.xe66
    

    Restart
    

     
    

    regards
    

     
    

    June
    

     
    
			
    

		
		
		
		
	
    
	
    
		
    
			
		
    
	
    

	            
                	
	
    
				
		                
                
                
                
                
                
                
        		
		
				
    
			
		
    
		
		 
		
		
     
    
	
    

    
			
    
			
    
		
    

		
    
	
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