hi team:
We have a block ADC32RF80EVM development board for use with the TSW14J56EVM. There are a few questions:
1. ADC32RF80 is 14 bits, the peak-to-peak value is 1.3V, and the full-scale count is 16384. But to use DDC, I set the 16-bit NCO frequency to 0, then one signal I is multiplied by 1, and the other Q is multiplied by 0. The output data I is 16-bit signals, the full-scale count bit is 65536, and the other Q is 0. I want to know how the 16-bit data corresponds to the 14-bit ADC data. 14-bit data is multiplied by 16-bit 1 and the highest two bits should be It is 0, the full scale should be 16384, how is it 65536? and When I input a signal with vpp=0.95V, the ADC sample data is almost 65536?
2. If i select the complex output, I is the signal, Q is 0. If you choose the real output, the output signal is not what I want, how is the complex to real module converted?
3. If it is fs=3Ghz, Divide-by-4 complex, Figure 97 shows the bandwidth 0.1*FS=300Mhz in adc32rf80.pdf, and OUTPUT BANDWIDTH (MHz) PER BAND is 600Mhz in Table 4. Why is it different? What is the meaning of the second bandwidth?
Thank you