The SLOW_CLK_IN on the PAN1325 module is labeled as Fail Safe. Does this mean that I do NOT hve to provide a clock? That would be the implication ....
Also, would the LDO 1.8V output supply enough current to run the VDD_IO? I see no real information regarding this option. I have been relying on the PAN1315 app sheet which seems a bit more complete but am not sure if I should trust it. Is there a more complete data sheet for the PAN1325 that gives full AC/DC specs and more information of OPTIONS, etc.?
Thanks for your help,
Mark