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AWR1642: DSS and MSS communication

Hitoshi Sugawara
Mastermind 18650 points
Part Number: AWR1642

Hi Champs,

 

I would like to know how to exchange the data between DSS and MSS.

For example, there are only two ways to send data from DSS to MSS?

 -Mailbox: DSS_ MBOX4BSS (2KB RAM)

Or

 - Handshake RAM(HSRAM) (32KB RAM)

 

Are the BANK 4 to 7 in DSS L3 memory able to be utilized as HSRAM?

Because it is written in the TRM (www.ti.com/lit/swru520) p.829, "L3 shared memory can also be used for the same purpose, ..."

 

Moreover, on p.827, it says that "256k bytes of memory is dedicated for the DSP, and the remaining memory can be shared between DSP and the Master Cortex-R4F at 128Kbyte granularity."

Does it mean that each 128Kbyte can be configure for MSS or DSS?

Is it possible to share one BANK for MSS and DSS?

( I would like to clarify if the data for DSS could be saved onto BANK 4 to 7 in DSS_L3_memory, MSS could write and read? )


According to the TRM p.418, it says that "Shared memory master allocation. Writing to each 8 bit field indicates the bank allocated to which master. 0x1 : DSS 0x2 : MSS TCMA 0x4 : MSS TCMB 0x8 : OCLA 0x10: BSS TCMA"
It seems that each BANK can not be allocate for several masters.

If DSS_L3_memory can be shared between DSS and MSS, please let me know how to configure and implement it.

 

Thank you very much for your kind help.

Best regards,

Hitoshi

  • 0
    TI__Guru 68170 points
    Hi Hitoshi San,
    Recommend memory to exchange data between DSS and MSS is Mailbox and HSRAM; mmw demo demonstrates these options only.

    HSRAM is separate memory out of L3 memory area. Let me rephrase TRM p.829 statement, "L3 shared memory can also be used for the same purpose, ...", an application can use HSRAM to transfer detected object list to MSS from DSP or as other option for transferring this data L3 memory can also be used where on another side MSS will read from L3 memory (this option may face arbitration).

    Based on TRM (figure 9-2) Bank 2 & 3 is dedicated to DSP (cannot be allocated to other cores) and Bank 4-7 can be allocated to either MSS/DSS. Each memory bank size is 128KB here.
    Just to clarify here that these memory banks are not physically shared b/w two cores, this memory bank can be allocated to either MSS or DSS.

    If you are intending to write data from DSS and read from MSS then the best way to use Mailbox/HSRAM as mentioned above.


    Regards,
    Jitendra
  • 0 in reply to Jitendra Gupta
    TI__Mastermind 18650 points
    Hi Jitendra,

    Could you please let us know blow:

    In TRM (figure 9-2), each bank is assigned to either MSS or DSS.
    As an example, assigning bank 4 to MSS, you can not access bank 4 from DSS.
    As another example, assigning bank 4 to DSS, you can not access bank 4 from MSS.
    So does that mean that you can not pass data between DSS and MSS using Bank 4?
    In conclusion, L3 memory can not be used for the same purpose as HSRAM. It is used as a dedicated memory of either DSS or MSS.

    Is it correct with the above understanding?

    If you can transfer data between DSS and MSS using Bank 4 (or 5, 6 or 7) of L3 memory, please tell me how to implement it. (Is it written in the manual?)

    Thank you for your kind support.
    Best regards,
    Hitoshi
  • 0 in reply to Hitoshi Sugawara
    TI__Guru 68170 points
    Hi,
    If you are seeking the memory option for data transfer between MSS and DSS then best option device provides as HSRAM and mailbox memory.

    And yes when memory is allocated to one core then other core may not have direct access to that memory. If bank 4 assigned to MSS then DSS can't access it but MSS being master of the device can access any type of memory, so it can access any L3 memory (if bank 4 is allocated to DSS).

    L3 memory (allocated or non-allocated) is not a preferred option for data trasnfer between MSS and DSS, as that memory may get overwritten by output of any FFT processing. But with all the precution (of memory data protection) taken by MSS and DSS cores, MSS can read data directly from L3 memory where it has different address (0x51000000) of that memory.


    Regards,
    Jitendra
  • 0 in reply to Hitoshi Sugawara
    TI__Guru 68170 points
    Hi Hitoshi,
    Can you confirm if this has answered your query or you need further info from us?

    Regards,
    Jitendra
  • 0 in reply to Jitendra Gupta
    TI__Mastermind 18650 points
    Hi Jiendra,
    Thank you for asking.
    It resolved our inquiry.
    Please close this.
    Best regards,
    Hitoshi