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TS3L501E: PHY Multiplexer Detection Questions regarding input standard

Part Number: TS3L501E

I am using the TS3L501E for multiplexing two ethernet paths to a single PHY chip. The PHY chip used is LAN8710A from Microchip.

I am currently testing one of the paths and I have issues with that.

Before using the TS3L501E we had an RJ45 connector and a magnet after that with its secondary centers tapped to 3.3v, and on the PHY side also the RX/TX signals are pulled up to 3.3v.

Now after placing TS3L501E the device is not discovered in the network.

My doubt is towards a few possible problems please give me advice that which one should be the cause, please note that as we have manufactured the boards I can not change many things all at once so it is crucial for me to know the main cause of the problem.

1- In PHY datasheet it is mentioned that: "LVCMOS Variable I/O voltage range: +1.6V to +3.6V" and in TS3L501E it says: "Differential (LVDS, LVPECL) Signal Switching" is there a problem here?

2- as the center taps of the magnet as well as the input of the PHY (8710 chip) both are pulled up to 3.3v, and the VDD of the TS3l501E is also 3.3v, I thought that some clipping might occur. As in the TS3L501E datasheet the recommended switching voltage is between 0 and VDD=3.3 v. 

If the problem is one of these what should I do? Does Ac coupling at input or output of the MUX help?

Thank you.

9 Replies

  • Hello Mike,

    There are a series of things that could be causing these issues.
    Could you share a schematic with us so that we can better evaluate what the problems might be?

    Could you also provide some scope captures of the output from our switch.

    To address question 1, our switch has the ability for LVDS (differential signals) but they do not have to be used in that manner. The reason we label this switch as Ethernet LAN switch is because the specs for it matches the applications. However, this switch can also be used in other applications as well.

    Another way to set up the switch can be seen in the previous E2E Post below:



    Thank you,

    Louie

  • In reply to Louie:

     Dear Louie

    Thanks for your reply.

    Attached is my handwritten approximate schematics. Please give advice.

  • In reply to Mike Brown24:

    Hello,

    The above looks reasonable to me, assuming that you are switching between network #2 and whatever is on the side of the magnetics.

    Louie

  • In reply to Louie:

    The problem is that when i have pulled up both sides of the TS3L501E to 3.3v, it means that the signals on these lines swing around 3.3v common mode voltage so they may go above 3.3v occasionally. Now due to the fact that the VDD of the TS3L501E is also 3.3v it can not switch signals above 3.3v level and/or it will deteriorate the signal. Right?
  • In reply to Mike Brown24:

    Yes, you are right. TS3L501E is not able to guarantee signal performance when the analog input or output signal is higher than VDD. 

    Fan Wang

  • In reply to Fan.Wang:

    Fan,
    thanks for your answer, I have two more questions to resolve my problem:
    1- In PHY datasheet it is mentioned that: "LVCMOS Variable I/O voltage range: +1.6V to +3.6V" and in TS3L501E it says: "Differential (LVDS, LVPECL) Signal Switching" . I am not sure if TS3L501E is suitable for my purpose. can you confirm that I can use TS3L501E for feeding this specific PHY?
    2- If i put series decoupling capacitors at both input/output ports of the TS3L501E (port A and B of the above sketch) to isolate the biasings on both ports, does it solve my problem? What will be the common mode voltage at input and output ports of the TS3L501E chip if both common mode voltage on the other sides of teh capacitors is still 3.3 volts.
    is it fundamentally ok to put these decoupling capacitors in signal path of the ethernet signal? or should i use dual magnets (transformers) on both sides.
    Thank you in advance
  • In reply to Mike Brown24:

    Hi Mike,

    Would you allow me to confirm one piece of information?

    Your PHY IOs can swing between 1.6V ~ 3.6V. This implies that the PHY's IO supply is 3.6V.

    Please correct me if I am wrong.

    Fan Wang

  • In reply to Fan.Wang:

    The PHY can bear up to 3.6v supply but in our system we are using standard 3.3v supply for it.
  • In reply to Mike Brown24:

    Hi Mike,

    Thanks for the information. If you use 3.3V for both PHY and LAN switch. PHY IO data can directly feed to LAN IO, since both will be within 3.3V range. In my opinioin, you do not need to bias Port A on your sketch.

    I do not know your magnetics profile. Isn't there a pin for DC bias voltage? If there isn't, a transferomer serves DC biasing purpose can be considerred at Port B on your sketch. Most PCB designers use that.

    Fan Wang

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