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Part Number: TIDA-01513
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In reply to LeonardEllis:
In reply to user6246671:
No worries, we can now review the attached file. Thank you for uploading and for using our forums :) We will first focus on the ISO barrier to the far right and cover the Digital Isolator and the Isolated Power supply.
For the Digital Isolator, it is completely fine to have 3.3V on the right side and Vdd5 on the left side . We recommend focusing on the ISO77XX family of isolators that come in multiple channel configurations. For example, the ISO7741 is a 4 channel isolator with 4 total channels and one reverse channel. The ISO7710 is a one channel isolator - 0 reverse channels and the 7762 is a 6 channel isolator with 2 reverse channels. You can use the datasheets for these parts to figure out who configuration and package suits your system the best.
For the Isolated Power supply, we need to clarify a few things:
Vdd5 on the left side is fine, but what about the Value of Vin on the right side? In the text box it says Vin = 5V, but want to make sure. If Vin = 5V, then will you have a local LDO on the right side to convert 5V down to 3.3V ?
After we clarify the power supply, I will request my colleagues to review the ADS portion of the schematic.
Thank you, Abhi
In reply to Abhi Aarey:
Hello , Abhi-san
Suppose the power supply has 12V, 5V, 3,3V on the right side.
12V to 5V is a switching regulator and 5V to 3.3V is an LDO.
I want to perform reinforced insulation from DC1000V.
The required clearance and creepage are as follows.
For material group I: Cl> 7.8mm, Cr> 10mm
If the creepage of the reinforced insulation cannot be satisfied, can it be regarded as double insulation with two times of basic insulation?
Please teach a schematic that meets these requirements.
Hi Dear user,
Thanks for clarifying the power supply side on the right side. 5V to 3.3V LDO clarifies this for me. We are now good on the power supply side.
If you want reinforced isolation and with a creepage > 10mm, then the simplest option would be to use the DWW package for your digital isolator. This package has >14mm creepage and clearance. Please check out our ISO7741-Q1 datasheet option, specifically the details and ratings for the DWW package. Section 7.6 of the datasheet would be a great place to start. [Link]
What are you using for generating the Isolated Power supply? Note that the supply path also needs to maintain the same creepage and clearance specs.
As you have pointed out, digital isolators can meet >10mm, but there are few options for power supply and photo MOS relay.
Therefore, I am thinking with the circuit image as attached. Is there any problem with such a configuration?
I looked at your circuit. It is good.
We can do some optimizations to this, if you are interested:
From the ISO7761, you have 6 signals coming out; 4 going into the ISOW7841 and 2 going into a driver + Photo MOS. It would actually be easier and simpler if you use a 2 channel isolator [ in the diagram it can be placed and laid out below the ISOW7841, same creepage and clearance, and used for control signals for S1, S2
Just for completeness, we have also written an article about this. Although we used an automotive application as an example , it is relevant here also - and is just shared as a reference for you later .
I think you are good to go on the Isolation side. I will mark this as REsolved, please let us know if you need further help on the ADS side of the schematic !
You are welcome.
Our colleagues will reach out to you during the work day next week (likely by Wednesday) , for suggestions on the ADS side.
I support many of the general purpose ADCs, including the ADS1118. I've looked over your schematic and only have a few comments.
- Make sure there is some bypass capacitance on VDD5 near the ADS1118. You'll want 0.1uF capacitance.
- Often, RC filtering is used on the analog inputs of the ADC. For the bandwidth, you'll want a value that's about 20x if the data rate of the ADC. If the data rate is 860SPS, then I would use a bandwidth of 17kHz. Start with a series 1kΩ resistor and you get that bandwidth with about 9nF of capacitance.
- What op-amps are being used for the measurement? I'd note that the offset and offset drift could be very significant to this measurement. Additionally, you want the buffer to have a much larger bandwidth than the filtering.
- The gain setting resistors (Rs1, Rs2, Rps2, Rns2) will be the largest factor in gain error for the measurement. You will need precision resistors to get good accuracy.
- How many SPI devices will be connected to the bus? Note that on the ADC side of the isolation, DOUT/DRDY goes hi-Z when /CS is high. However, when DOUT/DRDY goes across the isolation, the DOUT is always actively driven. You would need to connect /CS for that ADC to an enable of the DOUT/DRDY isolator, so that DOUT/DRDY goes hi-Z, if there are other devices on the SPI bus. This would prevent bus contention if all the DOUTs are tied together.
If you do construct this circuit for your application, please post back when the schematic is ready, and we can review it again.
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