CC1120 current draw while in eWOR rx sniff

How many preambles do you send and what is your datarate? This will set how long you can sniff without loosing a packet then how low your average current consumption can get.

  Iv started doing 8 as minimum number of preamble bits in PREAMBLE_CFG1 and data rate is 1.2kbps.  i seem to be having a new issue though dispite how well ewor was working before im having trouble with mine entering ewor now when i strobe SWOR after setting all registers i strobe SWOR and most the time SIMO goes high for a while then goes low into rx mode...   im trying to make a receiver low power that sniffs for packs then sends a small one back out and continues to sniff. before this problem it wouldn't always go back into ewor.  so my two issues is reliably entering ewor and current consumption any more help would be greatly appreciated ill also post my register settings just in case someone has time thank you.

unsigned char rfSettings[] = {

0x06,   // IOCFG3 GPIO3 IO Pin Configuration
0x14,   // IOCFG2 GPIO2 IO Pin Configuration
0x06,   // IOCFG1 GPIO1 IO Pin Configuration
0x06,   // IOCFG0 GPIO0 IO Pin Configuration
0x93,   // SYNC3 Sync Word Configuration [31:24]
0x0B,   // SYNC2 Sync Word Configuration [23:16]
0x51,   // SYNC1 Sync Word Configuration [15:8]
0xDE,   // SYNC0 Sync Word Configuration [7:0]
0x0B,   // SYNC_CFG1 Sync Word Detection Configuration Reg. 1
0x17,   // SYNC_CFG0
0x06,   // DEVIATION_M
0x03,   // MODCFG_DEV_E
0x1C,   // DCFILT_CFG
0x14,   // PREAMBLE_CFG1// changed from 14 to check ewor
0x2A,   // PREAMBLE_CFG0
0x40,   // FREQ_IF_CFG
0xC6,   // IQIC
0x14,   // CHANBW
0x46,   // MDMCFG1
0x05,   // MDMCFG0
0x43,   // SYMBOL_RATE2
0xA9,   // SYMBOL_RATE1
0x2A,   // SYMBOL_RATE0
0x20,   // AGC_REF 
0x19,   // AGC_CS_THR 
0x00,   // AGC_GAIN_ADJUST
0x91,   // AGC_CFG3
0x20,   // AGC_CFG2
0xA9,   // AGC_CFG1 // changed from A9
0xCF,   // AGC_CFG0 // changed from cF
0x20,   // FIFO_CFG // temp change from 20
0x00,   // DEV_ADDR
0x0B,   // SETTLING_CFG // changed from B
0x12,   // FS_CFG
0x08,   // WOR_CFG1
0x24,   // WOR_CFG0
0x10,   // WOR_EVENTO_MSB
0xC6,   // WOR_EVENTO_LSB
0x00,   // PKT_CFG2
0x05,   // PKT_CFG1
0x20,   // PKT_CFG0
0x0F,   // RFEND_CFG1
0x0C,   // RFEND_CFG0 
0x74,   // PA_CFG2
0x56,   // PA_CFG1
0x7E,   // PA_CFG0
0xFF,   // PKT_LEN

};

Start from the sniff mode example here: http://www.ti.com/lit/zip/swrc253 and go from there.

Iv looked over the examples although iv never gotten them to work there is a .h file that's never in the download if i copy the whole thing over and try and build with just one example.  however im missing where the trick is..   you can not just strobe SIDLE then SWOR then its not only not in ewor but not in rx every time iv tried...  sense my post i got ewor going again however when it receives a packet and sends one back out it wont go in ewor perhaps cause iv placed it in tx once also for once my transmitter that sends it the packet is set up to receive when not sending (it sends upon a button push) and it sends fine but no longer receives.  any suggestions as to why they wont communicate both ways or setting it back in ewor after a transmission? and yes they have the same sync word and preamble the transmitter has been in rx mode when not transmitting..

First, it would be easier to help if the question was easier to read. "iv" and lack of capital letter to start a sentence makes me want to skip your question since it take too long to actually understand what you are asking about.

- Which .h file are you referring to? The example should be self contained and run right out of the box.

- How do you know that the radio is not in eWOR? Note that if you pull CSn low the chip will exit eWOR.

- Have you checked that you don't have RX/TC FIFO under/overflow? It could easily be that you are unable to get into the correct state due to errors.

 I will have to try to run the example again to tell you which .h file was called and not there that caused the error.  Whenever I would add the example and build it, it would always cause an error asking for the .h file.  I would search the whole download folder for the header file and nothing would come up.  I will try and check and get back to you on that one.

I am assuming it is in eWOR for a couple of reasons.  The current (at the moment) is down to about 2mA but when it receives a packet (that I know it receives due to the Marc state as well as a logic analyzer) the current runs as high as 20mA for a short time.  I also strobe the SWOR before hand and the MISO line pulses low about every 0.1 second...   I think I was having a problem with a register not being high enough so it stayed in rx mode but fixed that issue.  The smart RF register settings for sniff mode are fallowed almost to a T and have been fallowed to a T a few times. 

Also I have been checking for RX/TX FIFO errors.  I store the status byte withe every  command over spi and I have created a function that checks that stored byte so if it had RX FIFO overflow for example it will flush the RX FIFO.  also when receiving or transmitting a packet I have set the RFEND_CFGx registers so that it will always go to IDLE then I use GPIO2 to pulse the MCU Wake up which triggers an ISR to check the Marc state if there are any errors they get taken care of then or if the RX/TX was successful I have to program move on to its next task which tends to be back in eWOR when im able to get it back there.

Also I just tried to build the example and the top error is that it can not open hal_int.h and when I search the folders it is not in there.

2 mA is IDLE, SWOR strobe should bring the chip down in SLEEP with much less current consumption with default settings.

If downloaded http://www.ti.com/lit/zip/swrc253, opened the cc1120_rx_sniff_mode.eww and rebuild the project without errors. Not sure how you manage to get an error here.

Not sure shy i was getting errors either..   before I had it transmitting and receiving just fine.  Then i got my rx sniff mode to work down to about 2mA.  Now for some reason i can not get it to receive.  Iv decided to go with the exact register settings from smartRF and the transmitter is transmitting fine (verified over logic analyse.. Every time it transmits the mcu wake up is pulsed and i read the marc state which is 40 for transmission successful).  now the receiver inst picking up anything.  I have checked and it shows its in RX mode no errors.  The registers are the same for both. Variable packet length, same preamble, same sync word,  same everything and neither should have anything set to flip the bits or data whitening or anything like that.  So it should work as before.  Also on the receiver side i just put it in rx via a rx strobe and check it every one second to make sure its still in RX mode.  Also MISO line goes high when a sync word is detected so i poll for that and not let it check the status if it is high...  Iv noticed it will drop an incoming packet if its disturbed by writing to it.

  Only evidence of what is going on is when i change RFEND_CFG0 to 0x01 rx terminates right away and marc state shows 0x02.  So that states RX termination based on CS or PQT.  Any suggestion?  is there anything I am over looking?

I will post some register setting to see if anyone notices anything but they are straight from smartRF

unsigned char rfSettings[] = {

0x06, // IOCFG3 GPIO3 IO Pin Configuration

0x14, // IOCFG2 GPIO2 IO Pin Configuration

0x06, // IOCFG1 GPIO1 IO Pin Configuration

0x06, // IOCFG0 GPIO0 IO Pin Configuration

0xD3, // SYNC3 Sync Word Configuration [31:24]

0x91, // SYNC2 Sync Word Configuration [23:16]

0xD3, // SYNC1 Sync Word Configuration [15:8]

0x91, // SYNC0 Sync Word Configuration [7:0]

0x0B, // SYNC_CFG1 Sync Word Detection Configuration Reg. 1

0x17, // SYNC_CFG0 Sync Word Length Configuration Reg. 0

0x06, // DEVIATION_M Frequency Deviation Configuration

0x03, // MODCFG_DEV_E Modulation Format and Frequency Deviation Configur..

0x1C, // DCFILT_CFG Digital DC Removal Configuration

0x18, // PREAMBLE_CFG1 Preamble Length Configuration Reg. 1

0x2A, // PREAMBLE_CFG0 Preamble Detection Configuration Reg. 0

0x40, // FREQ_IF_CFG RX Mixer Frequency Configuration

0xC6, // IQIC Digital Image Channel Compensation Configuration

0x08, // CHAN_BW Channel Filter Configuration

0x46, // MDMCFG1 General Modem Parameter Configuration Reg. 1

0x05, // MDMCFG0 General Modem Parameter Configuration Reg. 0

0x43, // SYMBOL_RATE2 Symbol Rate Configuration Exponent and Mantissa [1..

0xA9, // SYMBOL_RATE1 Symbol Rate Configuration Mantissa [15:8]

0x2A, // SYMBOL_RATE0 Symbol Rate Configuration Mantissa [7:0]

0x20, // AGC_REF AGC Reference Level Configuration

0x19, // AGC_CS_THR Carrier Sense Threshold Configuration

0x00, // AGC_GAIN_ADJUST RSSI Offset Configuration

0x91, // AGC_CFG3 Automatic Gain Control Configuration Reg. 3

0x20, // AGC_CFG2 Automatic Gain Control Configuration Reg. 2

0xA9, // AGC_CFG1 Automatic Gain Control Configuration Reg. 1

0xCF, // AGC_CFG0 Automatic Gain Control Configuration Reg. 0

0x00, // FIFO_CFG FIFO Configuration

0x00, // DEV_ADDR Device Address Configuration

0x03, // SETTLING_CFG Frequency Synthesizer Calibration and Settling Con..

0x12, // FS_CFG Frequency Synthesizer Configuration

0x08, // WOR_CFG1 eWOR Configuration Reg. 1

0x21, // WOR_CFG0 eWOR Configuration Reg. 0

0x00, // WOR_EVENT0_MSB Event 0 Configuration MSB

0x00, // WOR_EVENT0_LSB Event 0 Configuration LSB

0x00, // PKT_CFG2 Packet Configuration Reg. 2

0x05, // PKT_CFG1 Packet Configuration Reg. 1

0x20, // PKT_CFG0 Packet Configuration Reg. 0

0x0F, // RFEND_CFG1 RFEND Configuration Reg. 1

0x01, // RFEND_CFG0 RFEND Configuration Reg. 0 // i changed from 0x00 to 0x01 to see if there was problems //with pqt or CS and there must be

0x7F, // PA_CFG2 Power Amplifier Configuration Reg. 2

0x56, // PA_CFG1 Power Amplifier Configuration Reg. 1

0x7C, // PA_CFG0 Power Amplifier Configuration Reg. 0

0x13, // PKT_LEN Packet Length Configuration

0x00, // IF_MIX_CFG IF Mix Configuration

0x22, // FREQOFF_CFG Frequency Offset Correction Configuration

0x0B, // TOC_CFG Timing Offset Correction Configuration

0x00, // MARC_SPARE MARC Spare

0x00, // ECG_CFG External Clock Frequency Configuration

0x00, // CFM_DATA_CFG Custom frequency modulation enable

0x01, // EXT_CTRL External Control Configuration

0x00, // RCCAL_FINE RC Oscillator Calibration Fine

0x00, // RCCAL_COARSE RC Oscillator Calibration Coarse

0x00, // RCCAL_OFFSET RC Oscillator Calibration Clock Offset

0x00, // FREQOFF1 Frequency Offset MSB

0x00, // FREQOFF0 Frequency Offset LSB

0x77, // FREQ2 Frequency Configuration [23:16]

0x60, // FREQ1 Frequency Configuration [15:8]

0x00, // FREQ0 Frequency Configuration [7:0]

0x02, // IF_ADC2 Analog to Digital Converter Configuration Reg. 2

0xA6, // IF_ADC1 Analog to Digital Converter Configuration Reg. 1

0x04, // IF_ADC0 Analog to Digital Converter Configuration Reg. 0

0x00, // FS_DIG1 Frequency Synthesizer Digital Reg. 1

0x5F, // FS_DIG0 Frequency Synthesizer Digital Reg. 0

0x00, // FS_CAL3 Frequency Synthesizer Calibration Reg. 3

0x20, // FS_CAL2 Frequency Synthesizer Calibration Reg. 2

0x40, // FS_CAL1 Frequency Synthesizer Calibration Reg. 1

0x0E, // FS_CAL0 Frequency Synthesizer Calibration Reg. 0

0x28, // FS_CHP Frequency Synthesizer Charge Pump Configuration

0x03, // FS_DIVTWO Frequency Synthesizer Divide by 2

0x00, // FS_DSM1 FS Digital Synthesizer Module Configuration Reg. 1

0x33, // FS_DSM0 FS Digital Synthesizer Module Configuration Reg. 0

0xFF, // FS_DVC1 Frequency Synthesizer Divider Chain Configuration ..

0x17, // FS_DVC0 Frequency Synthesizer Divider Chain Configuration ..

0x00, // FS_LBI Frequency Synthesizer Local Bias Configuration

0x50, // FS_PFD Frequency Synthesizer Phase Frequency Detector Con..

0x6E, // FS_PRE Frequency Synthesizer Prescaler Configuration

0x14, // FS_REG_DIV_CML Frequency Synthesizer Divider Regulator Configurat..

0xAC, // FS_SPARE Frequency Synthesizer Spare

0x14, // FS_VCO4 FS Voltage Controlled Oscillator Configuration Reg..

0x00, // FS_VCO3 FS Voltage Controlled Oscillator Configuration Reg..

0x00, // FS_VCO2 FS Voltage Controlled Oscillator Configuration Reg..

0x00, // FS_VCO1 FS Voltage Controlled Oscillator Configuration Reg..

0xB4, // FS_VCO0 FS Voltage Controlled Oscillator Configuration Reg..

0x00, // GBIAS6 Global Bias Configuration Reg. 6

0x02, // GBIAS5 Global Bias Configuration Reg. 5

0x00, // GBIAS4 Global Bias Configuration Reg. 4

0x00, // GBIAS3 Global Bias Configuration Reg. 3

0x10, // GBIAS2 Global Bias Configuration Reg. 2

0x00, // GBIAS1 Global Bias Configuration Reg. 1

0x00, // GBIAS0 Global Bias Configuration Reg. 0

0x01, // IFAMP Intermediate Frequency Amplifier Configuration

0x01, // LNA Low Noise Amplifier Configuration

0x01, // RXMIX RX Mixer Configuration

0x0E, // XOSC5 Crystal Oscillator Configuration Reg. 5

0xA0, // XOSC4 Crystal Oscillator Configuration Reg. 4

0x03, // XOSC3 Crystal Oscillator Configuration Reg. 3

0x04, // XOSC2 Crystal Oscillator Configuration Reg. 2

0x03, // XOSC1 Crystal Oscillator Configuration Reg. 1

0x00, // XOSC0 Crystal Oscillator Configuration Reg. 0

0x00, // ANALOG_SPARE Analog Spare

0x00, // PA_CFG3 Power Amplifier Configuration Reg. 3

0x00, // WOR_TIME1 eWOR Timer Counter Value MSB

0x00, // WOR_TIME0 eWOR Timer Counter Value LSB

0x00, // WOR_CAPTURE1 eWOR Timer Capture Value MSB

0x00, // WOR_CAPTURE0 eWOR Timer Capture Value LSB

0x00, // BIST MARC Built-In Self-Test

0x00, // DCFILTOFFSET_I1 DC Filter Offset I MSB

0x00, // DCFILTOFFSET_I0 DC Filter Offset I LSB

0x00, // DCFILTOFFSET_Q1 DC Filter Offset Q MSB

0x00, // DCFILTOFFSET_Q0 DC Filter Offset Q LSB

0x00, // IQIE_I1 IQ Imbalance Value I MSB

0x00, // IQIE_I0 IQ Imbalance Value I LSB

0x00, // IQIE_Q1 IQ Imbalance Value Q MSB

0x00, // IQIE_Q0 IQ Imbalance Value Q LSB

0x80, // RSSI1 Received Signal Strength Indicator Reg. 1

0x00, // RSSI0 Received Signal Strength Indicator Reg.0

0x41, // MARCSTATE MARC State

0x00, // LQI_VAL Link Quality Indicator Value

0xFF, // PQT_SYNC_ERR Preamble and Sync Word Error

0x00, // DEM_STATUS Demodulator Status

0x00, // FREQOFF_EST1 Frequency Offset Estimate MSB

0x00, // FREQOFF_EST0 Frequency Offset Estimate LSB

0x00, // AGC_GAIN3 Automatic Gain Control Reg. 3

0xD1, // AGC_GAIN2 Automatic Gain Control Reg. 2

0x00, // AGC_GAIN1 Automatic Gain Control Reg. 1

0x3F, // AGC_GAIN0 Automatic Gain Control Reg. 0

0x00, // CFM_RX_DATA_OUT Custom Frequency Modulation RX Data

0x00, // CFM_TX_DATA_IN Custom Frequency Modulation TX Data

0x30, // ASK_SOFT_RX_DATA ASK Soft Decision Output

0x7F, // RNDGEN Random Number Generator Value

0x00, // MAGN2 Signal Magnitude after CORDIC [16]

0x00, // MAGN1 Signal Magnitude after CORDIC [15:8]

0x00, // MAGN0 Signal Magnitude after CORDIC [7:0]

0x00, // ANG1 Signal Angular after CORDIC [9:8]

0x00, // ANG0 Signal Angular after CORDIC [7:0]

0x08, // CHFILT_I2 Channel Filter Data Real Part [18:16]

0x00, // CHFILT_I1 Channel Filter Data Real Part [15:8]

0x00, // CHFILT_I0 Channel Filter Data Real Part [7:0]

0x00, // CHFILT_Q2 Channel Filter Data Imaginary Part [18:16]

0x00, // CHFILT_Q1 Channel Filter Data Imaginary Part [15:8]

0x00, // CHFILT_Q0 Channel Filter Data Imaginary Part [7:0]

0x00, // GPIO_STATUS General Purpose Input/Output Status

0x01, // FSCAL_CTRL Frequency Synthesizer Calibration Control

0x00, // PHASE_ADJUST Frequency Synthesizer Phase Adjust

0x00, // PARTNUMBER Part Number

0x00, // PARTVERSION Part Revision

0x00, // SERIAL_STATUS Serial Status

0x01, // MODEM_STATUS1 Modem Status Reg. 1

0x00, // MODEM_STATUS0 Modem Status Reg. 0

0x00, // MARC_STATUS1 MARC Status Reg. 1

0x00, // MARC_STATUS0 MARC Status Reg. 0

0x00, // PA_IFAMP_TEST Power Amplifier Intermediate Frequency Amplifier T..

0x00, // FSRF_TEST Frequency Synthesizer Test

0x00, // PRE_TEST Frequency Synthesizer Prescaler Test

0x00, // PRE_OVR Frequency Synthesizer Prescaler Override

0x00, // ADC_TEST Analog to Digital Converter Test

0x0B, // DVC_TEST Digital Divider Chain Test

0x40, // ATEST Analog Test

0x00, // ATEST_LVDS Analog Test LVDS

0x00, // ATEST_MODE Analog Test Mode

0x3C, // XOSC_TEST1 Crystal Oscillator Test Reg. 1

0x00, // XOSC_TEST0 Crystal Oscillator Test Reg. 0

};