Power consumption in the low Power mode

Hello,
What kind of HW Setup are you using (be specific)?
This pattern looks more like the device staying in PM2 then periodically waking up by using the sleep timer. But even in PM2 the current should be around 1 uA.

Hi Eirik,
Yes the current is higher than it should be in PM2 and if you see above, that's exactly my Question #1.
"What could cause the SOC to consume 17 or 22uA instead of 1uA (in P2) and 0.5uA (in P3)? What could I do to reduce it down to 0.5-1uA?"

And the measurement is at the battery source - instead of the battery I am using a DC Power Analyzer (Agilent N6705B). This 3V goes to TPS62730 which steps it down to 2.1. So when the battery (power supply in my setup) is providing 17uA, the SOC is consuming 3*17/2.1 = ~24uA. I don't have any other active load other than the CC2541. The 2.1V is only going to 8 Capacitors and then 2 DVDD pins and 6 AVDD pins.

Thanks,
Chintan

Hi Chintan,

First off, having the CCdebugger attached will draw current through the VDD_sense pin of the debugger. Secondly, you did not answer Eirik´s question on what HW you are using. Is this a TI kit, or your own board? Typically excessive current consumption in low power modes is caused by other devices (like sensors) being turned on, pull-ups or -downs incorrectly being enabled, etc. Lastly, you must also remember to set the TPS in bypass mode when going into PMx.

Cheers,
Fredrik

Thanks Fredrik for your response.
This is my own board and not a TI kit.
About the other devices (like sensors) - I mentioned that in my earlier post. I do not have any active devices. The only thing I have connected to the 2.1V is the AVDD and DVDD. One thing I interpreted in the user guide was to configure all unused pins as outputs and that's what I have done.
To isolate and reduce power, I have disconnected everything and don't have anything left. Based on the user guide, my interpretation is that the IOs hold their state and they shouldn't be drawing the power.

But please do suggest how I should configure the IOs to reduce the power.

Even with the incorrect pull-ups and power draw, the other question still remains - what is waking up the SOC every 1.24msec?

Thanks,
Chintan

Hello,
What kind of SW are you running? Have you tried to use the light weight code examples: CC2541/43/44/45 Peripherals Software Examples ?
Have you tried to completely bypass the DCDC (run without)?

Chintan Kanuga said:

what is waking up the SOC every 1.24msec?

This is of course dependent on what SW you are using. I would follow Eirik´s recommendation to run a very simple SW example to verify the PM2/3 current consumption.

Are you configuring the DCDC for bypass when you go to LPM?

Thanks Eirik,
I get linker error when running TI sample codes -
"Error[e16]: Segment ISTACK (size: 0xc0 align: 0) is too long for segment definition. At least 0xe more bytes needed. The problem occurred while processing the segment placement command "-Z(IDATA)ISTACK+_IDATA_STACK_SIZE#08-_IDATA_END", where at the moment of placement the available memory ranges were "IDATA:4e-ff" "
Trying to solve this will take away my focus from the power problem.

Although I have looked at the sample codes and am trying to modify my code to simplify as much as possible.

There is some timer that I have in my code - which keeps waking up the SOC every 1.25msec. Could you suggest how I could isolate and find out what timer I have that I still have to disable? Would turning the DCDC off, somehow disable the timers?

I tried looking at the rework of removing the DCDC - but it isn't trivial. But I will keep that in mind and try that. But if the problem is with my code that has some timer running, do you think removing the DCDC is worthwhile experiment - considering it being not a trial task?

Regards,
Chintan

Thanks Fredrik,
Yes I tried bypassing the DCDC in the LPM. As you indicated the SOC waking up every 1.24msec is something in my code - maybe some timer that stays on. Would bypassing the DCDC somehow disable the timers OR atleast prevent the SOC from waking up every so often?

I added a push-button to the board and added a code to switch the DCDC into Bypass mode. But it takes 4 or 6 pushbutton presses before the SOC stops waking up. So whatever this timer is that wakes up the SOC takes 4 or 6 button presses to get disabled. And even with the same exact code, the number of times I have to press the button is not deterministic. And I am using the same button presses to turn advertising ON/OFF - so I know that the button presses are being recognized by the SOC.

Thanks,
Chintan

FYI...have you seen the power consumption app note? www.ti.com/.../litabsmultiplefilelist.tsp

I would recommend verifying you can do this correctly on TI hardware. Then port the same software to run on your hardware.

Hello,
Does this solve your problem:
e2e.ti.com/.../1104076;pi239031348scroll=false
e2e.ti.com/.../1069645;pi239031348scroll=false

Just run in debug mode and look at the timer registers to see whats going on. If you have enabled any tiemr interrupt routines (ISR) you can also add a break point there to figure out your setup.

Enabling bypass on the regulator will not do anything besides putting the regulator in bypass mode. That is, the output will be equal to the input and the quiescent current of the regulator is reduced to a few uA.