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TRF7960A: Unable to clear IRQ status(0x80) after the dummy read.

Chee Yang Eng
Prodigy 130 points
Other Parts Discussed in Thread: TRF7960A

Hi All,


I am connecting TRF7960ATB to my mcu throught SPI interface.

When the IRQ line goes high, I read the IRQ status by 0x6C and also apply the dummy read on it. I am getting 0x80(End of TX). The IRQ line goes Low after that. However, when I apply the second read on the IRQ status(0x6C) almost immediately after that, I am still getting 0x80. The End of TX doesn't get clear by the first IRQ status read like it is mention on the document.


Is there anyway I can debug this? The next IRQ line event, I am getting 0x81 which indicate "No response" and "End of TX".


Thanks!

Regards

  • 0
    TI__Mastermind 38660 points

    Hello,

    Sorry for the delay in response. Are you also applying the reset FIFO(0x8F) command with dummy clock after the dummy read? Have a look at figure 6-21 in the TRF760A datasheet.  Let me know if this fixes your problem.

    www.ti.com/.../trf7960a

  • 0 in reply to Eddie LaCost
    Prodigy 10 points

    I am also working with Chee Yang on this development effort.

    Yes, the sequence looks like this:
    <--- IRQ line high
    ---> SS low
    ---> Read IRQ status (value = 0x80)
    ---> 8 dummy clocks
    <--- IRQ line low
    ---> SS high

    ---> SS low
    ---> Write reset command (0x8F)
    ---> 1 dummy clock
    ---> SS high

    After this point, I can read IRQ status repeatedly if I want (including dummy read) - the value is always 0x80. Eventually, the IRQ line will be re-asserted by the TRF7960A, and at that point reading IRQ status gives 0x81. The bit7 of the IRQ status register is never cleared.

    The scope is showing a fairly low SPI clock rate of 200kHz, so I don't think we are forcing it too hard. I also confirmed that the reset command dummy clock is equal in width to the normal clock pulses and that there are no MOSI transitions during any of the dummy clocks.

  • 0 in reply to Logan McDougall51
    Prodigy 130 points

    I started to wonder if there is something different at the circuit between TRF7960A EVM vs TRF7960A TB. I tried to mimic the data setting from TRF7060A EVM board, but I still get the same result. Are there any different between these two boards that SW need to set or handle differently?

  • 0 in reply to Chee Yang Eng
    TI__Mastermind 38660 points
    The software settings between the EVM and TB board should be the same. On the TB board, you could disable sys_clk, but it should not cause any issue to leave it enabled. Do you have logic analyzer captures which show this behaviour, so I can evaluate further? Also, what is your SPI clock rate?