Other Parts Discussed in Thread: TEST2
hello
i am using a CC1101 to transmit this kind of frame : {0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x00,0x00,0x00,0x00,0x1F,0xFF,0xFF,0xFF,0xFB,0x23,....,}
i use another CC1101 to receive it . when i configure (SYNC1,SYNC0) = (0x55,0x00) or (0x55,0x50) or (0x50,0x00) the CC1101 succeed to find it and receive the frame
but when it configure i configure (SYNC1,SYNC0) = (0x00,0x00) or (0xFF,0xFF) or (0x00,0xFF) or (0xFF,0xFB) or (0x0F,0xFF) the CC1101 do not detect it
PS all my register config :
halRfWriteReg(IOCFG2,0x0D); //GDO2 Output Pin Configuration : Serial Data Output
halRfWriteReg(IOCFG0,0x06); //GDO0 Output Pin Configuration : Asserts when sync word has been sent / received, and de-asserts at the end of the packet.
halRfWriteReg(FIFOTHR,0x47); //0x4? adc with bandwith< 325khz
halRfWriteReg(SYNC1,0x55); //01010101
halRfWriteReg(SYNC0,0x00); //00000000
halRfWriteReg(PKTCTRL1,0x80);//Preamble quality estimator threshold=16 ; APPEND_STATUS=0; no addr check
halRfWriteReg(PKTCTRL0,0x00);//fix length , no CRC
halRfWriteReg(PKTLEN,38);
halRfWriteReg(FSCTRL1,0x08); //Frequency Synthesizer Control
halRfWriteReg(FREQ2,0x10); //Frequency Control Word, High Byte Base frequency = 433.82
halRfWriteReg(FREQ1,0xAF); //Frequency Control Word, Middle Byte
halRfWriteReg(FREQ0,0x75); //Frequency Control Word, Low Byte
halRfWriteReg(MDMCFG4,0xF6); //Modem Configuration RX filter BW = 58Khz
halRfWriteReg(MDMCFG3,0x83); //Modem Configuration 26M*((256+83h)*2^6)/2^28 = 2.4kbps
halRfWriteReg(MDMCFG2,0x02); //Modem Configuration 2-FSK; no Manchester ; 16/16 sync word bits detected
halRfWriteReg(MDMCFG1,0x00); //Modem Configuration num preamble 2=>0 , Channel spacing_exp
halRfWriteReg(MDMCFG0,0x00); /*# MDMCFG0 Channel spacing = 25Khz*/
halRfWriteReg(DEVIATN,0x15); //5.157471khz
halRfWriteReg(MCSM1,0x0F); //CCA always ; default mode RX
halRfWriteReg(MCSM0,0x18); //Main Radio Control State Machine Configuration
halRfWriteReg(FOCCFG,0x1D); //Frequency Offset Compensation Configuration
halRfWriteReg(BSCFG,0x1C); //Bit Synchronization Configuration
halRfWriteReg(AGCCTRL2,0xC7);//AGC Control
halRfWriteReg(AGCCTRL1,0x00);//AGC Control
halRfWriteReg(AGCCTRL0,0xB2);//AGC Control
halRfWriteReg(WORCTRL,0xFB); //Wake On Radio Control
halRfWriteReg(FREND1,0xB6); //Front End RX Configuration
halRfWriteReg(FSCAL3,0xE9); //Frequency Synthesizer Calibration
halRfWriteReg(FSCAL2,0x2A); //Frequency Synthesizer Calibration
halRfWriteReg(FSCAL1,0x00); //Frequency Synthesizer Calibration
halRfWriteReg(FSCAL0,0x1F); //Frequency Synthesizer Calibration
halRfWriteReg(TEST2,0x81); //Various Test Settings link to adc retention
halRfWriteReg(TEST1,0x35); //Various Test Settings link to adc retention
halRfWriteReg(TEST0,0x09); //Various Test Settings link to adc retention