Hello forum,
Hopefully I will not spend much of your time since my problem sounds small but I am struggling to find clear instructions in the datasheet. We are using a CC1125 with Sniff Mode (eWOR) enabled, running with the internal crystal. The register configurations are listed below. We want to stop using the internal crystal and instead we are using GPIO3 of CC1125 in order to input a 32KHz external clock. So far, we cannot get the radio to work by modifying the following 4 registers which seem to be the only ones impacting the selection of the crystal used according to the datasheet unless I have missed something. Any help is more than welcome…
Changes to register values in order to switch to external crystal (according to user guide/datasheet):
IOCFG3 = 0x30 (GPIO3_CFG = 48)
EXT_CTRL = 0x02 (EXT_32K_CLOCK_EN = 1)
WOR_CFG0 = 0x21 (RC_PD = 1 and DIV_256HZ_EN =1) also tried with (DIV_256HZ_EN =0)
Register values with default, working configuration (using internal clock):
{ CC112X_IOCFG3, 24 }, // LNA/PA
{ CC112X_IOCFG2, 26 }, // RX0TX1
{ CC112X_IOCFG1, 0xB0 },
{ CC112X_IOCFG0, 0x06 }, // SYNC RXTX
{ CC112X_SYNC_CFG0, 0x14 },
{ CC112X_SYNC_CFG1, 0x0B },
{ CC112X_PREAMBLE_CFG1, 0x34 }, // 0x34->30bytes preamble, 0x30-> 24bytes preamble, 0x2C->12bytes preamble, 0x28->8bytes preamble - If you change this update the WOR settings too!
{ CC112X_DEVIATION_M, 0xA3 },
{ CC112X_MODCFG_DEV_E, 0x0A },
{ CC112X_DCFILT_CFG, 0x1C },
{ CC112X_FREQ_IF_CFG, 0x33 },
{ CC112X_IQIC, 0xC6 },
{ CC112X_CHAN_BW, 0x10 },
{ CC112X_MDMCFG0, 0x05 },
{ CC112X_MDMCFG1, 0x80 | 0x40 | 8 | 6 | 0 },
{ CC112X_AGC_GAIN_ADJUST, -77 },
{ CC112X_SYMBOL_RATE2, 0x3F },
{ CC112X_SYMBOL_RATE1, 0x75 },
{ CC112X_SYMBOL_RATE0, 0x10 },
{ CC112X_AGC_REF, 0x20 },
{ CC112X_AGC_CFG1, 0xA0 },
{ CC112X_FIFO_CFG, 0x00 },
{ CC112X_SETTLING_CFG, 0x03 | 0x18 },
{ CC112X_FS_CFG, 0x12 },
{ CC112X_PKT_CFG0, 0x0 },
{ CC112X_PKT_LEN, NumberPacketBytes },
{ CC112X_IF_MIX_CFG, 0x00 },
{ CC112X_FREQOFF_CFG, 0x30 },
{ CC112X_FREQ2, 0x56 },
{ CC112X_FREQ1, 0xEC },
{ CC112X_FREQ0, 0x28 },
{ CC112X_IF_ADC0, 0x05 },
{ CC112X_FS_DIG1, 0x00 },
{ CC112X_FS_DIG0, 0x5F },
{ CC112X_FS_CAL0, 0x0E },
{ CC112X_FS_DIVTWO, 0x03 },
{ CC112X_FS_DSM0, 0x33 },
{ CC112X_FS_DVC0, 0x17 },
{ CC112X_FS_PFD, 0x50 },
{ CC112X_FS_PRE, 0x6E },
{ CC112X_FS_REG_DIV_CML, 0x14 },
{ CC112X_FS_SPARE, 0xAC },
{ CC112X_XOSC5, 0x0E },
{ CC112X_XOSC3, 0xC7 },
{ CC112X_XOSC1, 0x07 },
{ CC112X_RFEND_CFG1, 0x0f }, // end rx to idle
{ CC112X_RFEND_CFG0, 0x9 }, // end tx to into idle, term on bad & on CS
{ CC112X_WOR_CFG0, 0x00 }, // high resmode,
{ CC112X_WOR_CFG1, 0x08 },
{ CC112X_WOR_EVENT0_MSB, 0x6 }, // These may need tuning
{ CC112X_WOR_EVENT0_LSB, 0x3e /*116*/},
{ CC112X_PKT_CFG1, 0x45 }, // Whiten, CRC & Status on end - enable soon to add whitening
{ CC112X_PKT_CFG2, 0x10 }, // Enable LBT
{ CC112X_DEVIATION_M, 0xf8 },
{ CC112X_PREAMBLE_CFG1, 0x34 }, // 30bytes preamble
{ CC112X_MODCFG_DEV_E, 0x08 },
{ CC112X_CHAN_BW, 0x19 },
{ CC112X_SYMBOL_RATE2, 0x3f },
{ CC112X_AGC_REF, 0x20 },
{ CC112X_AGC_CS_THR, CC_MIN_SIGNAL },
{ CC112X_WOR_CFG0, 0x20 }, // 0x20->30,24,12,8bytes preamble
{ CC112X_WOR_EVENT0_MSB, 0x18 }, // 0x18->30bytes preamble, 0x13->24bytes preamble, 0x09->12bytes preamble, 0x06->8bytes preamble
{ CC112X_WOR_EVENT0_LSB, 0x8F }, // 0x8F->30bytes preamble, 0x90->24bytes preamble, 0x92->12bytes preamble, 0x3E->8bytes preamble