Compiler/CC1310: How to change the predefine section use for the TiRtos to different address since they are in conflict with custom section

Hi Steve,

Could you share the the log output you are getting from the linker? Also, have you looked at this wiki page?

processors.wiki.ti.com/.../Processor_SDK_RTOS:_TI_RTOS_Tips_And_Tricks

Hi

Find below the output that I get, It look like the section DEFAULT overlaps my stuff, I tried to look to the link provided but it is quite complex for beginner on CCS. I was used to IAR.

<Linking>
warning #10247-D: creating output section ".vtable_ram" without a SECTIONS specification
"C:/Users/scorbin/workspace_v8/tirtos_builds_CC1310_LAUNCHXL_release_ccs/Debug/configPkg/linker.cmd", line 700: warning #10096-D: specified address lies outside memory map
error #10264: DEFAULT memory range overlaps existing memory range SHARERAM_REGION
error #10264: DEFAULT memory range overlaps existing memory range SRAM_REGION
"C:/Users/scorbin/workspace_v8/tirtos_builds_CC1310_LAUNCHXL_release_ccs/Debug/configPkg/linker.cmd", line 699: warning #10096-D: specified address lies outside memory map
error #10264: DEFAULT memory range overlaps existing memory range BOOT1_REGION
error #10264: DEFAULT memory range overlaps existing memory range HEADER_REGION
error #10264: DEFAULT memory range overlaps existing memory range APPLICATION_REGION
error #10264: DEFAULT memory range overlaps existing memory range ENCRYPTER_REGION
error #10264: DEFAULT memory range overlaps existing memory range FOOTER_REGION
error #10264: DEFAULT memory range overlaps existing memory range BOOT2_REGION
error #10264: DEFAULT memory range overlaps existing memory range BOOT_INFO_REGION
error #10264: DEFAULT memory range overlaps existing memory range MERGER_INFO_REGION
error #10264: DEFAULT memory range overlaps existing memory range PLATFORM_INFO_REGION
error #10264: DEFAULT memory range overlaps existing memory range APPLICATION_INFO_REGION
error #10263: DEFAULT memory range has already been specified
error #10264: DEFAULT memory range overlaps existing memory range DEFAULT
error #10264: DEFAULT memory range overlaps existing memory range SHARERAM_REGION
error #10264: DEFAULT memory range overlaps existing memory range SRAM_REGION
error #10010: errors encountered during linking; "WD1_App.out" not built

SHARERAM is a specific ram by me that is located in 0x20000200, length 0f 0x10

Here below is a portion of my linker file that f=define all region

MEMORY
{
//INTVECT_REGION (RX) : origin = __ICFEDIT_intvec_start__, length = __ICFEDIT_intvec_size__
/* Boot1 memory region 0x000000000 to 0x00001fff */
BOOT1_REGION (RX) : origin = __BOOT1_start__, length = __BOOT1_size__

/* Application header 0x00002000 to 0x0000200F */
HEADER_REGION (RX) : origin = __APP_HEADER_start__, length = __APP_HEADER_size__

/* Application Code Area 0x00002010 to 0x0001EFDF */
APPLICATION_REGION (RX) : origin = __APPLICATION_code_start__, length = __APPLICATION_code_size__

/* Application encrypter memory region 0x0001EFE0 to 0x0001EFEF */
ENCRYPTER_REGION (RX) : origin = __APP_ENCRYPTER_start__, length = __APP_ENCRYPTER_size__

/* Application footer memory region 0x0001EFF0 to 0x0001EFFF */
FOOTER_REGION (RX) : origin = __APP_FOOTER_start__, length = __APP_FOOTER_size__

/* Boot2 memory region 0x0001F000 to 0x0001FE7F */
BOOT2_REGION (RX) : origin = __BOOT2_start__, length = __BOOT2_size__

/* Boot Info memory region 0x0001FE80 to 0x0001FE8F */
BOOT_INFO_REGION (RX) : origin = __BOOT_INFO_start__, length = __BOOT_INFO_size__

/* Merger Info memory region 0x0001FE90 to 0x0001FECF */
MERGER_INFO_REGION (RX) : origin = __MERGER_INFO_start__, length = __MERGER_INFO_size__

/* Platform Info memory region 0x0001FED0 to 0x0001FEFF */
PLATFORM_INFO_REGION (RX) : origin = __PLATFORM_INFO_start__, length = __PLATFORM_INFO_size__

/* Application Info memory region 0x0001FF00 to 0x0001FF7F */
APPLICATION_INFO_REGION (RX): origin = __APPLICATION_INFO_start__, length = __APPLICATION_INFO_size__


/* RAM Region */
/* Share ram memory area 0x20000200 to 0x2000020f*/
SHARERAM_REGION (RWX) : origin = __SHARE_RAM_start__, length = __SHARE_RAM_size__

/* General Sram memroy area 0x20000210 to 0x20004fff*/
SRAM_REGION (RWX) : origin = __SRAM_start__, length = __SRAM_size__
}

SECTIONS
{
.text : > APPLICATION_REGION
.TI.ramfunc : {} load=APPLICATION_REGION, run=SRAM_REGION, table(BINIT)
.const : > APPLICATION_REGION
.constdata : > APPLICATION_REGION
.rodata : > APPLICATION_REGION
.cinit : > APPLICATION_REGION
.pinit : > APPLICATION_REGION
.init_array : > APPLICATION_REGION
.emb_text : > APPLICATION_REGION
.ccfg : > CCFG_REGION
.app_header : > HEADER_REGION
.encrypter : > ENCRYPTER_REGION
.app_footer : > FOOTER_REGION
.bootinfo : > BOOT_INFO_REGION
.mergerinfo : > MERGER_INFO_REGION
.platforminfo : > PLATFORM_INFO_REGION
.appinfo : > APPLICATION_INFO_REGION

.shareram : > SHARERAM_REGION
.data : > SRAM_REGION
.bss : > SRAM_REGION
.sysmem : > SRAM_REGION
.nonretenvar : > SRAM_REGION


/* Heap buffer used by HeapMem */
.priheap : {
__primary_heap_start__ = .;
. += HEAPSIZE;
__primary_heap_end__ = .;
} > SRAM_REGION align 8

.stack : > SRAM_REGION (HIGH)
}

Hi Steve,

Are you basing this of an existing linker file, just what changes have you personally made (there seems to be several custom regions in the linker file)?

What is it you want to achieve with the custom region, is the custom region(s?) in RAM? If you are doing multiple custom flash regions, I would recommend you start small and add them in one by one to see where you are hitting the wall in the linker.

Hi

I started from an example linker file than I add my custom region.

What I'm doing is I built an on board bootloader that is used by my pc software application to upgrade a certain are in flash via uart. These section are some area that I used to validate the application along with some common area that are sue either by my boot loader and my application. most of these section are in flash with one exception that is the shareram that is in ram.

This application is working with IAR, I been recommanded to switch to CCS in order to ease my transition for SDK Upgrade.

I compile my boot without any issue ( The boot doesn't use TiRTOS), than I tried to compile my application that use TIRtos and got these errors. We can easily see that the many section created by the automatic linker file of the tirtos become in conflict with my section?

Hi Steve,

What I'm trying to figure out is if the linker file you started from is from a TI example or not so that I can give it a close look. That is also why I wanted to pin down just what changes you did to the linker file (and what was already there from the example).

You could typically adjust the placement of the kernel by using the .cfg file. One think I can think of directly is the reset vector table and the default location of it. How you can relocate this are explained in the API documentation:

dev.ti.com/.../index.html

This is also practiced in most BLE project (for example) that support the BIM (bootloader used for OAD).

found in the zip the original cmd file from uartecho example with rtos and my cmd file thaty I modified

Hi Steven,

So I have had the time to go over the linker file and project and pinned down your issues. The main issue with the "DEFAULT memory range overlaps existing memory range ..." is related to the placement of the TI-RTOS kernel resetVectors. As you have moved the application FLASH space to 0x00002010, you also need to reflect this in the TI-RTOS configuration.

You can do this by adding the following to the bottom of the .cfg file:
Program.sectMap[".resetVecs"].loadAddress = 8208;

Alternatively, adding "m3Hwi.resetVectorAddress = 0x00002010;" should also work.

Compiling the project, there was also some regions that needed to be corrected in size but this should be quite straight forward what needs to be increased. SRAM_V_TABLE_REGION was one of the the regions that needed to be resized, this because there is some needs from the TI-RTOS to place things at the beginning of RAM.

Placement in the beginning (around 0x20000100) of the RAM is needed by the TI-RTOS kernel as the ROM expects fixed RAM locations for certain modules, thus the SRAM_V_TABLE_REGION section (in this case) need to be larger then the actual vtable as it will need to fit the TI-RTOS specific placements as well.

I hope this information is enough for you to get it compiling on your size, let me know if there is any remaining issues after this!

Hi

I tried it and have same issue, I succeed to fix the vtable issue( I think)

Can you point where I find the .cfg file to modified? I fouind one but not sure it ios the good one