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Hi Team,
According to the THS3217 data sheet, the output stage of the device shows overshoot for a step response. My customer has a circuit that shows similar and they'd like to minimize the overshoot.
Here are some design requirements:
Their current setup is: Rf=140, Rg=34.8, the overshoot is ~15%
They can reduce the overshoot by increasing the gain, but the noise level has gone up.
What would you recommend a scheme that can reproduce a square wave without overshoot at maximum bandwidth possible?
Preference is a positive gain, but a negative gain is also okay.
Thanks,
Mitchell
Morning Mitchell
This is of course the classic case of controlling the phase margin to tradeoff speed for overshoot. Can you provide a TINA file? Design goals? Options
1. you are coming from the D2S output?- you could consider an equalizing filter between it and the OPS input
2. Scaling the R's up around the OPS will overcompensate - but increase the noise.
3. Scope waveform would help, not likely but you could also be slew limiting.
In any case, from the full setup - the 1st thing to do is check phase margin in the OPS (and overshoot out of the D2S) - those ideal plots of peaking and overshoot vs phase margin are in this article
- then setting up for a CFA LG is described in #7. I spent quite some time tuning the inverting input impedance on this model for the OPS to get correct SSFR vs gain etc. Would need that to go further,
And I just remembered Mitchell, I did generate a plot relating small signal frequency response peaking to % overshoot for an ideal 2nd order response. So if you ran that sim you should be able to predict the overshoot. This shows up in the most recent "The Signal Sped Up" talking mainly about slew limited edge rate issues. So if this is applicable, that 15% overshoot is only 1dB peaking (Butterworth flat is actually 4.3% step overshoot). It would not take much increase in Rf value (and Rg for the same gain) to flatten that out I would think.