Part Number: ADC12DJ3200 Other Parts Discussed in Thread: LMK04828 , LMX2594 Hi team,
The customer uses their own design board, the FPGA is 420T, the refclk and the reference clock of the FPGA is generated by LMK04828, the LMK connects the LMX2594 to output…
Part Number: ADC12DJ3200 Other Parts Discussed in Thread: LMK04828 , LMX2594 嗨,团队,
我使用自己的设计板,FPGA是420T,FPGA的参考时钟和参考时钟由LMK04828产生,LMK连接LMX2594输出ADC器件时钟和参考时钟。示波器可以观察产生的时钟信号。
J MODE1,ILA观察到的同步信号被拉低,但xillnx IP核tdata没有数据输入(K28.5),并且ADC上的前景校准无法完成,0x6A总是读取0C。 …
Part Number: ADC12DJ3200 Hi,
Pls clarify the convertor operation in JMODE14 - Fs at 3.2 GSPS
Targeted signal at 2.6 plus/minus 50 MHz.
What rate the 4 lanes to be operated - dual channel operation required.
Regards,
Rajesh khanna
Part Number: ADC12DJ3200 Dear Madam, Sir,
We are using ADC12DJ3200 and would like to know the downtime duration of a foreground calibration (+ offset calibration) of the ADC. The datasheet says:
Foreground calibration always runs on power-up and the user…
Part Number: ADC12DJ3200 Other Parts Discussed in Thread: TSW14J57EVM Hi All,
Is their Python libraries or scripts available for operating and automating ADC12DJ3200 and its Eval Board TSW14J57EVM and any specific examples for the same? Thanks for the…
Part Number: ADC12DJ3200
Hi,
We have a custom board with ADC12DJ3200 ADC and Kintex UltraScale FPGA from Xilinx. We are using JMODE 0.
I am using the KCU105 reference design for JMODE 0, but the FFT is not fine.
So I tested short transport test pattern…
Part Number: DAC39J84EVM Other Parts Discussed in Thread: ADC12DJ3200EVM , , LMK04828 Hello,
I am using the DAC39J84EVM in conjunction with the ADC12DJ3200EVM to operate as data converters respectively in transmitter and receiver of a bespoke optical communication…
Part Number: ADC12DJ4000RF Other Parts Discussed in Thread: ADC12DJ3200 , Hello,
We currently use the ADC12DJ3200 (at 2.5GSPS). We are looking at alternatives since is not in stock. How compatible is the 4000RF to the 3200? Would it be close to a drop-in…
Hi Ayana,
Can you please provide me your register writes. Also can send me your schematic for ADC and clock for the ADC.
Can also program register address 0x29 to 0x60 and then read the SYSREF_POS register(0x2C-0x2E) 10 time and send the results.
After…
Part Number: ADC12DJ3200 Hello, when we are debugging adc12dj3200 chip, in JMODE0, 6Gsps, lane rate = 12Gbps mode, the following situations will occur:
1. In ramp test code mode, the rx_sync signal output by JESD204B core will be pulled down for a short…