Part Number: ADC12DJ3200 Hi team,
I am using ADC12DJ3200 Ibis model as Transmitter in JESD204B lanes. I am using TX_ami along with nport_typ_xxxx_RI and DAx.s4p.
As of my understanding DAx shall be used for x-th channel of converter A, and DBx.s4p for x-th…
Part Number: ADC12DJ3200 Other Parts Discussed in Thread: LMX2594 , LMX2595 Hi,
I'm using the ADC12DJ3200 combined with a LMX2595RHAR.
ADC CLK: 3.2GHz
GSPS: 12.8
SYSREF = 40MHz
K = 4
FPGA CLK = 320 MHZ
My Startup routine is following:
0x0200, 0x…
Part Number: ADC12DJ3200 Dear all,
we have a problem aligning the lanes in JESD204B IF. We use JMODE7 in the ADC12DJ3200 EVM with 8 lanes (2 channels, 8 bit per ch). When we run the ramp test, we see the lanes aligned but not in the operative mode, when…
Part Number: ADC12DJ3200 Hello,
Our customer used ADC12DJ3200 and read the register 0x208= 0110_1100, it indicated that the PLL is lock, but the register 0x2C1 is 0001_1000 which indicated that PLL lost lock alarm. Why?
In addition, the FG calibration…
Part Number: ADC12DJ3200 Hi team,
The typical application description in chapter 8.2 of the ADC12DJ3200 datasheet using balun requires type 1:2, and the typical application is tcm2-43x. The reference design hsp001-ADC12dj3200evm schematic clock pins balun…
Part Number: ADC12DJ3200 hi,
I would like to use the Long Transport Test Pattern, however I cannot follow the calculation of the data.
so I'm using JMODE16 , K=20
I get:
Frame0 Frame1
DA0 (I0) = 0x0003 0x0002
DA1 (I1) = 0x0002 0x0005
DA2 (Q0) =…
Part Number: ADC12DJ3200 Hi Team,
I am using ADC12DJ3200 in my design. I want to confirm about the output lane rate for the JMODE 12.
Case1: As mentioned in the datasheet the lane rate would be Devclk multiplied by the factor R. and R is derived as 1…
Hi Rohit,
Can you make sure the your lane mapping from ADC to FPGA is correct? Please note lane jesd lanes the polarity has been swapped for easy routing. see the table below.
Regards,
Neeraj
Part Number: ADC12DJ3200 Other Parts Discussed in Thread: TPS7A92 Hi team,
Due to stringent requirements for noise performance, one of our customers needs to use 2 LDOs to power digital voltage VD11 and analog voltage VA11, rather than use common 1.1VDC…